Seo, Jae-Sun

XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks

Yin, S., Jiang, Z., Seo, J.-S., & Seok, M. (2020) · IEEE Journal of Solid-State Circuits

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 429

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks

Sun, X., Yin, S., Peng, X., Liu, R., Seo, J.-S., & Yu, S. (2018) · 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 246

Benchmarking TinyML Systems: Challenges and Direction

Banbury, C. R., Reddi, V. J., Lam, M., Fu, W., Fazel, A., Holleman, J., Huang, X., Hurtado, R., Kanter, D., Lokhmotov, A., et al. (2020) · arXiv

IoT and Edge/Fog ComputingAdvanced Neural Network Applications

Cited by 216

High-Throughput In-Memory Computing for Binary Deep Neural Networks With Monolithically Integrated RRAM and 90-nm CMOS

Yin, S., Sun, X., Yu, S., & Seo, J.-S. (2020) · IEEE Transactions on Electron Devices

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 171

Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays

Kulkarni, S. R., Kadetotad, D. V., Yin, S., Seo, J.-S., & Rajendran, B. (2019) · 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 23