Jiang, Hongwu

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip Training

Peng, X., Huang, S., Jiang, H., Lu, A., & Yu, S. (2021) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 317

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Su, J.-W., Si, X., Chou, Y.-C., Chang, T.-W., Huang, W.-H., Tu, Y.-N., Liu, R., Lu, P.-J., Liu, T.-W., Wang, J.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 189

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Li, W., Sun, X., Huang, S., Jiang, H., & Yu, S. (2022) · IEEE Journal of Solid-State Circuits

Advanced Memory and Neural ComputingAdvanced Neural Network Applications

Cited by 77

A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays

Jiang, H., Li, W., Huang, S., & Yu, S. (2022) · 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 58