Su, Jian-Wei

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., Pan, T., et al. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 207

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Su, J.-W., Si, X., Chou, Y.-C., Chang, T.-W., Huang, W.-H., Tu, Y.-N., Liu, R., Lu, P.-J., Liu, T.-W., Wang, J.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 189

A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme

Chen, W.-H., Lin, W.-J., Lai, L.-Y., Li, S., Hsu, C.-H., Lin, H.-T., Lee, H.-Y., Su, J.-W., Xie, Y., Sheu, S.-S., et al. (2017) · 2017 IEEE International Electron Devices Meeting (IEDM)

Advanced Memory and Neural ComputingFerroelectric and Negative Capacitance Devices

Cited by 73