CoChat
Sign Up
Cited by 334VLSI and FPGA Design TechniquesCopper Interconnects and ReliabilityInterconnection Networks and Systems

The DOI matches its Crossref record, with a small difference in title or year; 1 of the 1 references it cites were found in a registry or an index.

Performance optimization of VLSI interconnect layout

Cong, Jason, He, Lei, Koh, Cheng-Kok, Madden, Patrick H.·1996·Integration
DOI 10.1016/s0167-9260(96)00008-9
Open this paper in CoChat — free account

Overview

Integrity signals

Registry

Crossref · 10.1016/s0167-9260(96)00008-9

Cites

1 of 1 references verified0 citation errors · 0 not checkable

Statistics

Recomputing p-values needs the paper’s full text.

Verification

Claims the paper makes

We couldn’t retrieve this paper’s full text, so its claims and self-check weren’t run. The registry and citation checks still apply.

Citations

Cites

Show all 1 references

Research works printed but not linked: 59

  1. Rubinstein, 1983, Signal delay in RC tree networks, IEEE Trans. Comput.-Aided Des., CAD-2, 202, 10.1109/TCAD.1983.1270037 · DOI
  2. Elmore, 1948, The transient response of damped linear networks with particular regard to wide-band amplifiers, J. Appl. Phys., 19, 55, 10.1063/1.1697872 · DOI
  3. Cong, 1995, Optimal wiresizing under the distributed Elmore delay model, IEEE Trans. Comput.-Aided Des., 14, 321, 10.1109/43.365123 · DOI
  4. Cong, 1994, Simultaneous driver and wire sizing for performance and power optimization, IEEE Trans. Very Large Scale Integration (VLSI) Systems, 2, 408, 10.1109/92.335010 · DOI
  5. Nagel, 1975, SPICE2: a computer program to simulate semiconductor circuits, Technical Report ERL-M520
  6. Cong, 1996, Optimal wire sizing for interconnects with multiple sources, ACM Trans. on Design Automation of Electronic Systems, 10.1145/238997.239018 · DOI
  7. Cong, 1995, UCLA Tech. Report 95-00031
  8. Pillage, 1990, Asymptotic waveform evaluation for timing analysis, IEEE Trans. Comput.-Aided Des., 9, 352, 10.1109/43.45867 · DOI
  9. Ratzlaff, 1994, RICE: rapid interconnect circuit evaluation using AWE, IEEE Trans. Comput.-Aided Design of Integrated Circuits and Systems, 13, 763, 10.1109/43.285250 · DOI
  10. Yu, 1995, Exact moment matching model of transmission lines and application to interconnect delay estimation, IEEE Trans. Very Large Scale Integration (VLSI) Systems, 3, 311, 10.1109/92.386230 · DOI
  11. Zhou, 1994, A simplified synthesis of transmission lines with a tree structure, Int. J. Analog Integrated Circuits Signal Processing, 19, 10.1007/BF01673903 · DOI
  12. Kahng, 1996, Analytical delay model for VLSI interconnects under ramp input, UCLA CS Dept. TR-960015
  13. Hedenstierna, 1987, CMOS circuit speed and buffer optimization, IEEE Trans. Comput.-Aided Des., 270, 10.1109/TCAD.1987.1270271 · DOI
  14. Qian, 1994, Modeling the effective capacitance for the RC interconnect of CMOS gates, IEEE Trans. Comput.-Aided Des. Integrated Circuits Systems, 13, 1526, 10.1109/43.331409 · DOI
  15. Prim, 1957, Shortest connecting networks, Bell System Tech. J., 31, 1398
  16. Lee, 1980, Voronoi diagrams in l1 (l∞) metrics with 2-dimensional storage applications, SIAM J. Comput., 9, 200, 10.1137/0209017 · DOI
  17. Hwang, 1992, Steiner tree problems, Networks, 22, 55, 10.1002/net.3230220105 · DOI
  18. Hanan, 1966, On Steiner's problem with rectilinear distance, SIAM J. Appl. Math., 14, 255, 10.1137/0114025 · DOI
  19. Hwang, 1976, On Steiner minimal trees with rectilinear distance, SIAM J. Appl. Math., 30, 104, 10.1137/0130013 · DOI
  20. Ho, 1990, New algorithms for the rectilinear Steiner tree problem, IEEE Trans. Comput.-Aided Design, 9, 185, 10.1109/43.46785 · DOI
  21. Kahng, 1992, A new class of iterative Steiner tree heuristics with good performance, Trans. Comput.-Aided Des., 11, 893, 10.1109/43.144853 · DOI
  22. Georgakopoulos, 1987, The 1-Steiner tree problem, J. Algorithms, 8, 122, 10.1016/0196-6774(87)90032-0 · DOI
  23. Minoux, 1990, Efficient greedy heuristics for Steiner tree problems using reoptimization and supermodularity, INFOR, 28, 221
  24. Bern, 1988, Two probabilistic results on rectilinear Steiner trees, Algorithmica, 3, 191, 10.1007/BF01762114 · DOI
  25. Borah, 1994, An edge-based heuristic for Steiner routing, IEEE Trans. Comput.-Aided Des., 13, 1563, 10.1109/43.331412 · DOI
  26. Cong, 1991, Performance-driven global routing for cell based ICs, IEEE Int. Conf. Computer Design, 170
  27. Cong, 1992, Provably good performance-driven global routing, IEEE Trans. Comput.-Aided Des., 11, 739, 10.1109/43.137519 · DOI
  28. Dijkstra, 1959, A note on two problems in connection with graphs, Numer. Math., 1, 269, 10.1007/BF01386390 · DOI
  29. Rao, 1992, The rectilinear Steiner arboresence problem, Algorithmica, 277, 10.1007/BF01758762 · DOI
  30. Cong, 1995, Performance driven routing with multiple sources, 10.1109/ISCAS.1995.521486 · DOI
  31. Sakurai, 1983, Approximation of wiring delay in MOS-FET LSI, IEEE J. Solid-State Circuits, 4, 418, 10.1109/JSSC.1983.1051966 · DOI
  32. Dreyfus, 1972, The Steiner problem in graphs, Networks, I, 195
  33. Boese, 1995, Near-optimal critical sink routing tree constructions, IEEE Trans. Comput.-Aided Des., 14, 1417, 10.1109/43.476573 · DOI
  34. Lin, 1975, An optimized output stage for MOS integrated circuits, IEEE J. Solid-State Circuits, SC-10, 106
  35. Zhou, 1996, On the optimal drivers for high-speed low power ICs, Int. J. High Speed Electron. System, 10.1142/S0129156496000128 · DOI
  36. Veendrick, 1984, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE J. Solid-State circuits, SC-19, 468, 10.1109/JSSC.1984.1052168 · DOI
  37. Heulser, 1991, Transistor sizing for large combinational digital CMOS circuits, Integration VLSI J., 10, 185
  38. Chen, 1991, iCOACH: a circuit optimization aid for CMOS high-performance circuits, Integration VLSI J., 10, 155, 10.1016/S0167-9260(06)80015-5 · DOI
  39. Ecker, 1980, Geometric programming: methods, computations and applications, SIAM Rev., 22, 338, 10.1137/1022058 · DOI
  40. Shyu, 1988, Optimization based transistor sizing, IEEE J. Solid-State Circuits, 400, 10.1109/4.1000 · DOI
  41. Sapatnekar, 1993, An exact solution to the transistor sizing problem for CMOS circuits using convex optimization, IEEE Trans. Comput.-Aided Des., 1621, 10.1109/43.248073 · DOI
  42. Hoppe, 1990, Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area and dynamic power dissipation, IEEE Trans. Comput.-Aided Des., 9, 237, 10.1109/43.46799 · DOI
  43. Hinsberger, 1992, A cell-based approach to performance optimization of fanout-free circuits, IEEE Trans. Comput.-Aided Des., 11, 1317, 10.1109/43.170993 · DOI
  44. Li, 1994, Strongly NP-hard discrete gate-size problems, IEEE Trans. Comput.-Aided Des., 13, 1045, 10.1109/43.298040 · DOI
  45. Cong, 1995, UCLA Computer Science, Tech. Report 95-00046
  46. Edahiro, 1991, Minimum skew and minimum path length routing in VLSI layout design, NEC Res. Dev., 32, 569
  47. Chao, 1992, Zero skew clock routing with minimum wire length, IEEE Trans. Circuits Systems, 39, 799, 10.1109/82.204128 · DOI
  48. Cong, 1995, Minimum-cost bounded-skew clock routing, Vol. 1, 215
  49. Wann, 1983, Asynchronous and clocked control structures for VLSI based interconnection networks, IEEE Trans. Comput., C-32, 284, 10.1109/TC.1983.1676220 · DOI
  50. Cong, 1993, Matching-based methods for high-performance clock routing, IEEE Trans. Comput.-Aided Des., 12, 1157, 10.1109/43.238608 · DOI
  51. Wu, 1992, Effective buffer insertion of clock tree for high-speed VLSI circuits, Microelectro. J., 23, 291, 10.1016/0026-2692(92)90026-W · DOI
  52. Fishburn, 1990, Clock skew optimization, IEEE Trans. Comput., 39, 945, 10.1109/12.55696 · DOI
  53. Nair, 1989, Generation of performance constraints for layout, IEEE Trans. Comput.-Aided Des., 8, 860, 10.1109/43.31546 · DOI
  54. Lin, 1989, SILK: a simulated evolution router, IEEE Trans. Comput.-Aided Des., 8, 1108, 10.1109/43.39072 · DOI
  55. Khoo, 1995, An efficient multilayer MCM router based on four-via routing, IEEE Trans. Comput.-Aided Des., 1277, 10.1109/43.466343 · DOI
  56. Khoo, 1995, Transistor sizing for minimizing power consumption of CMOS circuit under delay constraint, Proc. Int. Symp. on Lower Power Design, 167
  57. Chuang, 1995, Timing and area optimization for standard-cell VLSI circuit design, IEEE Trans. Comput.-Aided Design, 308, 10.1109/43.365122 · DOI
  58. Martinez, 1993, Timing model accuracy issues and automated library characterization, IFIP Trans. A (Comput. Sc. Technol.), A-22, 413
  59. Smith, 1979, Steiner trees, Steiner circuits and the interference problem in building design, Eng. Optim., 30, 15, 10.1080/03052157908902401 · DOI

Cited by

Sorted by citations

Metadata

Authors
Cong, J., He, L., Koh, C.-K., & Madden, P. H.
Affiliations
University of California, Los Angeles (US)
Corresponding author
Cong, Jason
ORCID
Venue
Integration
Publisher
Elsevier BV
Published
1996-11
Volume
21
Issue
1-2
Pages
1-94
ISSN
0167-9260 (ISSN-L)
DOI
10.1016/s0167-9260(96)00008-9
OpenAlex
W2076265641
Cited by
334
References
1
Citations by year
2025: 1 · 2024: 2 · 2023: 1 · 2022: 1 · 2021: 4 · 2019: 6 · 2018: 5 · 2017: 4 · 2016: 3 · 2015: 3 · 2014: 6 · 2013: 6 · 2012: 10
FWCI
24.24
Type
journal article
Language
en
Open access
closed
Licence
Locations
Integration (publishedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
  • Physical Sciences › Materials Science › Electronic, Optical and Magnetic Materials › Copper Interconnects and Reliability
  • Physical Sciences › Computer Science › Computer Networks and Communications › Interconnection Networks and Systems
Keywords
topology optimization, wirelength minimization, delay reduction, device sizing, buffer insertion, clock routing, physical design

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review