FPGA Realization of a Novel Hyperchaos Augmented Image Encryption Algorithm

Abstract

With the rapid growth of multimedia communication, protecting image data has become increasingly critical. This article proposes a novel 3‐stage hyperchaos‐based augmented image encryption technique (3SHAIET) that utilizes a three‐stage process with chaotic systems of increasing dimensionality (e.g., six‐dimensional [6D], 8D, and 9D) to enhance security against cryptographic attacks. At each stage, the image is converted into a 1D bit‐stream array, encrypted using dynamically generated S‐boxes, and XORed with keys derived from the chaotic systems, ensuring high sensitivity to initial conditions and strong diffusion and confusion properties. To achieve real‐time performance, the algorithm is realized on a field‐programmable gate array (FPGA), leveraging hardware acceleration for the lowest possible latency encryption. The FPGA realization is shown to provide a 165 times improvement in encryption rate over its corresponding software implementation. Experimental results demonstrate the algorithm’s robustness, with an extremely large key space of 2 5475 and resistance to statistical (PSNR of 8.11 dB, MAE of 81.74, and entropy of 7.999) and differential attacks (NPCR of 99.6216% and UACI of 32.0534%). Additionally, the resulting encrypted images’ bit‐streams successfully pass all National Institute of Standards and Technology (NIST) randomness tests, further validating the algorithm’s security. These results make the proposed 3SHAIET algorithm a highly efficient and secure solution for modern multimedia systems. The objective of 3SHAIET is to jointly maximize cryptographic strength (via multistage hyperchaotic keys and dynamic S‐boxes) and real‐time efficiency (via FPGA realization) for secure multimedia transmission and storage.