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A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects
Abstract
In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.
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“the proposed GSI-NWM has better immunity against short-channel effects [67,68].”
From Analytical modeling and doping optimization for enhanced analog performance in a Ge/Si interfaced nanowire MOSFET (2023) · cites this paper as [68]
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Cited by
Sorted by citations
Das, A., Rewari, S., Kanaujia, B. K., Deswal, S. S., & Gupta, R. S. (2023) · Physica Scripta · doi:10.1088/1402-4896/acde16 · Cited by 49
Metadata
- Authors
- Ramezani, Z., & Orouji, A. A.
- Affiliations
- Semnan University (IR)
- Corresponding author
- Orouji, Ali A.
- Venue
- International Journal of Electronics
- Publisher
- Informa UK Limited
- Published
- 2017-07-27
- Pages
- 1-14
- ISSN
- 0020-7217 (ISSN-L)
- 1362-3060
- OpenAlex
- W2735638895
- Cited by
- 31
- References
- 0
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 2 · 2023: 4 · 2022: 2 · 2021: 6 · 2020: 8 · 2019: 4 · 2018: 2
- FWCI
- 1.59
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- International Journal of Electronics (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor materials and devices
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Keywords
- double-gate MOSFET, short-channel effects, SOI MOSFET, off-state current, drain-induced barrier lowering, gate-induced drain leakage, threshold voltage, lateral electric field, carrier diffusion, low-power VLSI design
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