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Cited by 168

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Critical charge concepts for CMOS SRAMs

Dodd, P.E., Sexton, F.W.·1995·IEEE Transactions on Nuclear Science

Abstract

The dramatic effects of external circuit loading on the heavy-ion-induced charge-collection response of a struck transistor are illustrated using three-dimensional mixed-mode simulations. Simulated charge-collection and SEU characteristics of a CMOS SRAM cell indicate that, in some cases, more charge call be collected at sensitive nodes from strikes that do not cause upset than from strikes that do cause upset. Computations of critical charge must take into account the time during which charge is collected, not simply the total amount of charge collected. Model predictions of the incident linear energy transfer required to cause upset agree well with measured data for CMOS SRAMs, without parameter adjustments. The results show the absolute necessity of treating circuit effects in any realistic device simulation of single-event upset (SEU) in SRAMs.

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Metadata

Authors
Dodd, P. E., & Sexton, F. W.
Venue
IEEE Transactions on Nuclear Science
Published
1995-12
Volume
42
Issue
6
Pages
1764-1771
ISSN
  • 0018-9499 (ISSN-L)
  • 1558-1578
OpenAlex
W2138111642
Cited by
168
References
0
FWCI
5.75
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: Critical charge concepts for CMOS SRAMs. https://app.cochat.ai/papers/10.1109/23.488777
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Dodd, P. E., & Sexton, F. W. (1995). Critical charge concepts for CMOS SRAMs. IEEE Transactions on Nuclear Science. https://doi.org/10.1109/23.488777

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