The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.
An analog neural network processor with programmable topology
Abstract
The architecture, implementation, and applications of a special-purpose neural network processor are described. The chip performs over 2000 multiplications and additions simultaneously. Its data path is particularly suitable for the convolutional topologies that are typical in classification networks, but can also be configured for fully connected or feedback topologies. Resources can be multiplexed to permit implementation of networks with several hundreds of thousands of connections on a single chip. Computations are performed with 6 b accuracy for the weights and 3 b for the neuron states. Analog processing is used internally for reduced power dissipation and higher density, but all input/output is digital to simplify system integration. The practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition. This network contains over 130000 connections and was evaluated in 1 ms.>
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Globally trained, variable-size TDNN/HMM hybrids have been used for speech recognition and online handwriting recognition.
“Globally trained, variablesize TDNN/HMM hybrids have been used for speech recognition and online handwriting recognition [67], [77], [89], [90].”
From Gradient-based learning applied to document recognition (1998) · cites this paper as [89]
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Cites
Phoneme recognition using time-delay neural networks
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LeCun, Y., Bengio, Y., & Hinton, G. (2015) · Nature · doi:10.1038/nature14539 · Cited by 84,126
Self-citationGradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
Self-citationConvolutional networks and applications in vision
LeCun, Y., Kavukcuoglu, K., & Farabet, C. (2010) · Proceedings of 2010 IEEE International Symposium on Circuits and Systems · doi:10.1109/iscas.2010.5537907 · Cited by 2,213
Self-citationISAAC: A Convolutional Neural Network Accelerator with In-Situ Analog Arithmetic in Crossbars
Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2016.12 · Cited by 775
CNP: An FPGA-based processor for Convolutional Networks
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Metadata
- Authors
- Boser, B. E., Sackinger, E., Bromley, J., Le Cun, Y., & Jackel, L. D.
- Affiliations
- AT&T (United States) (US)
- Venue
- IEEE Journal of Solid-State Circuits
- Published
- 1991
- Volume
- 26
- Issue
- 12
- Pages
- 2017-2025
- ISSN
- 0018-9200 (ISSN-L)
- OpenAlex
- W1999497791
- Cited by
- 142
- References
- 1
- Citations by year
- 2026: 1 · 2025: 2 · 2024: 4 · 2023: 7 · 2022: 2 · 2021: 2 · 2020: 21 · 2019: 7 · 2018: 8 · 2017: 3 · 2016: 3 · 2015: 5 · 2014: 6 · 2013: 3 · 2012: 3
- FWCI
- 4.48
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Journal of Solid-State Circuits (publishedVersion)
- Open Research Online (The Open University) (acceptedVersion)
- HAL (submittedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Analog and Mixed-Signal Circuit Design
- Physical Sciences › Computer Science › Artificial Intelligence › Neural Networks and Applications
- Keywords
- convolutional neural networks, classification networks, fully connected networks, feedback network, digital-to-analog conversion, low power consumption, optical character recognition, VLSI implementation
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