The DOI matches its Crossref record; 16 of the 16 references it cites were found in a registry or an index.
VLSI architectures for video compression-a survey
Abstract
The paper presents an overview on architectures for VLSI implementations of video compression schemes as specified by standardization committees of the ITU and ISO. VLSI implementation strategies are discussed and split into function specific and programmable architectures. As examples for the function oriented approach, alternative architectures for DCT and block matching will be evaluated. Also dedicated decoder chips are included Programmable video signal processors are classified and specified as homogeneous and heterogenous processor architectures. Architectures are presented for reported design examples from the literature. Heterogenous processors outperform homogeneous processors because of adaptation to the requirements of special, subtasks by dedicated modules. The majority of heterogenous processors incorporate dedicated modules for high performance subtasks of high regularity as DCT and block matching. By normalization to a fictive 1.0 /spl mu/m CMOS process typical linear relationships between silicon area and through-put rate have been determined for the different architectural styles. This relationship indicates a figure of merit for silicon efficiency.>
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Cites
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Self-citationA new algorithm to compute the discrete cosine Transform
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Digital pictures: representation and compression
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Predictive Coding Based on Efficient Motion Estimation
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Metadata
- Authors
- Pirsch, P., Demassieux, N., & Gehrke, W.
- Venue
- Proceedings of the IEEE
- Published
- 1995
- Volume
- 83
- Issue
- 2
- Pages
- 220-246
- ISSN
- 0018-9219 (ISSN-L)
- OpenAlex
- W2127711920
- Cited by
- 294
- References
- 16
- FWCI
- 38.00
- Type
- journal article
- Language
- en
- Open access
- closed
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- Pirsch, P., Demassieux, N., & Gehrke, W. (1995). VLSI architectures for video compression-a survey. Proceedings of the IEEE. https://doi.org/10.1109/5.364465
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