The DOI matches its Crossref record; 6 of the 6 references it cites were found in a registry or an index.
Outstanding Bit Error Tolerance of Resistive RAM-Based Binarized Neural Networks
Open accessAbstract
Resistive random access memories (RRAM) are novel nonvolatile memory technologies, which can be embedded at the core of CMOS, and which could be ideal for the in-memory implementation of deep neural networks. A particularly exciting vision is using them for implementing Binarized Neural Networks (BNNs), a class of deep neural networks with a highly reduced memory footprint. The challenge of resistive memory, however, is that they are prone to device variation, which can lead to bit errors. In this work we show that BNNs can tolerate these bit errors to an outstanding level, through simulations of networks on the MNIST and CIFAR10 tasks. If a standard BNN is used, up to 10-4bit error rate can be tolerated with little impact on recognition performance on both MNIST and CIFAR10. We then show that by adapting the training procedure to the fact that the BNN will be operated on error-prone hardware, this tolerance can be extended to a bit error rate of 4 × 10-2. The requirements for RRAM are therefore a lot less stringent for BNNs than more traditional applications. We show, based on experimental measurements on a RRAM HfO2technology, that this result can allow reduce RRAM programming energy by a factor 30.
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Binarized neural networks are highly robust to weight errors, which in many cases do not change neuron activation.
“Nevertheless, binarized neural networks are highly robust to weight errors, which in many cases do not change neuron activation33,34.”
From Powering AI at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell (2024) · cites this paper as [33]
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Cites
LeCun, Y., Bengio, Y., & Hinton, G. (2015) · Nature · doi:10.1038/nature14539 · Cited by 84,126
Gradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
In-memory computing with resistive switching devices
Ielmini, D., & Wong, H.-S. P. (2018) · Nature Electronics · doi:10.1038/s41928-018-0092-2 · Cited by 2,298 · cited 2×
“Nevertheless, despite their outstanding qualities, emerging memories are prone to device variation [4], [10], which can cause bit errors.”
BackgroundXNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks
Sun, X., Yin, S., Peng, X., Liu, R., Seo, J.-S., & Yu, S. (2018) · 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) · doi:10.23919/date.2018.8342235 · Cited by 246
In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep Neural Networks
Bocquet, M., Hirztlin, T., Klein, J.-O., Nowak, E., Vianello, E., Portal, J.-M., & Querlioz, D. (2018) · 2018 IEEE International Electron Devices Meeting (IEDM) · doi:10.1109/iedm.2018.8614639 · Cited by 99
Self-citationSu, F., Chen, W.-H., Xia, L., Lo, C.-P., Tang, T., Wang, Z., Hsu, K.-H., Cheng, M., Li, J.-Y., Xie, Y., et al. (2017) · 2017 Symposium on VLSI Technology · doi:10.23919/vlsit.2017.7998149 · Cited by 69
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Research works printed but not linked: 17
- 10.1088/1361-6463/aad954 · DOI
- zhang, 2017, A 130nm 1mb hfox embedded rram macro using self-adaptive peripheral circuit system techniques for 1.6 x work temperature range, Proc A-SSCC, 173
- 10.23919/VLSIC.2017.8008533 · DOI
- 10.1109/ASPDAC.2018.8297384 · DOI
- tang, 2017, Binary convolutional neural network on rram, Proc ASP-DAC, 782
- 10.1109/IEDM.2016.7838348 · DOI
- 10.1109/JPROC.2003.811709 · DOI
- chang, 2014, 19.4 embedded 1mb reram in 28nm cmos with 0.27-to-1v read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme, Proc ISSCC, 332
- 10.1109/ISCAS.2017.8050341 · DOI
- 10.1109/JPROC.2015.2437616 · DOI
- 10.1109/JPROC.2018.2790840 · DOI · Paper page
- 10.1007/978-3-319-46493-0_32 · DOI · Paper page
- 10.1038/d41586-018-01683-1 · DOI
- 10.1109/IRPS.2018.8353675 · DOI
- 10.1109/JSSC.2018.2841824 · DOI
- abadi, 2016, Tensorflow: a system for large-scale machine learning, OSDI, 16, 265
- krizhevsky, 2009, Learning multiple layers of features from tiny images, Tech Rep
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Sorted by citations
Jebali, F., Majumdar, A., Turck, C., Harabi, K.-E., Faye, M.-C., Muhr, E., Walder, J.-P., Bilousov, O., Michaud, A., Vianello, E., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-44766-6 · Cited by 58
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Metadata
- Authors
- Hirtzlin, T., Bocquet, M., Klein, J.-O., Nowak, E., Vianello, E., Portal, J.-M., & Querlioz, D.
- Affiliations
- Université Paris-Sud (FR)
- Centre National de la Recherche Scientifique (FR)
- Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR)
- Venue
- 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
- Publisher
- IEEE
- Published
- 2019-03
- Pages
- 288-292
- OpenAlex
- W2932447952
- Cited by
- 51
- References
- 6
- Citations by year
- 2025: 4 · 2024: 3 · 2023: 12 · 2022: 10 · 2021: 12 · 2020: 7 · 2019: 3
- FWCI
- 12.73
- Type
- conference paper
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- HAL (submittedVersion, other-oa)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Keywords
- resistive random access memory, binary neural networks, device variability, in-memory computing, non-volatile memory, hafnium oxide, image classification
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