Return-to-Non-Secure Vulnerabilities on ARM Cortex-M TrustZone: Attack and Defense
Abstract
ARM Cortex-M is one of the most popular microcontroller architectures designed for embedded and Internet of Things (IoT) applications. To facilitate efficient execution, it has some unique hardware optimization. In particular, Cortex-M TrustZone has a fast state switch mechanism that allows direct control-flow transfer from the secure state program to the non-secure state userspace program. In this paper, we demonstrate how this fast state switch mechanism can be exploited for arbitrary code execution with escalated privilege in the non-secure state by introducing a new exploitation technique, namely return-to-non-secure (ret2ns). We experimentally confirmed the feasibility of four variants of ret2ns attacks on two Cortex-M hardware systems. To defend against ret2ns attacks, we design two address sanitizing mechanisms that have negligible performance overhead.
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Address masking places non-secure user-space and kernel-space programs within predefined memory regions, providing an additional layer of security by limiting exploitable address spaces.
“Address masking involves placing non-secure user-space and kernel-space programs within predefined memory regions, providing an additional layer of security via limiting the exploitable address spaces.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [148]
Recent research studies have proposed address sanitizing and address masking to overcome several vulnerabilities of TEEs.
“Recent research studies [148, 149] have proposed several methods, such as address sanitizing and address masking to overcome several vulnerabilities of TEEs.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [148]
Address sanitizing leverages the Memory Protection Unit in non-secure states to verify privilege levels during state transitions, thereby preventing unauthorized access.
“Address sanitizing leverages the Memory Protection Unit (MPU) in non-secure states to verify privilege levels during state transitions, thereby preventing unauthorized access.”
From Confidential Computing Across Edge‐To‐Cloud for Machine Learning: A Survey Study (2025) · cites this paper as [148]
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References 16 · Cited by 8
- Authors
- Ma, Z., Tan, X., Ziarek, L., Zhang, N., Hu, H., & Zhao, Z.
- Affiliations
- University at Buffalo, State University of New York (US)
- Washington University in St. Louis (US)
- Venue
- 2023 60th ACM/IEEE Design Automation Conference (DAC)
- Publisher
- IEEE
- Published
- 2023-07-09
- Pages
- 1-6
- ISSN
- 0738-100X (ISSN-L)
- OpenAlex
- W4386763927
- Cited by
- 8
- References
- 16
- Citations by year
- 2026: 2 · 2025: 4 · 2024: 2
- FWCI
- 1.42
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- ACM/IEEE Design Automation Conference (DAC) (publishedVersion)
- Funders
- National Science Foundation
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Security and Verification in Computing
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Computer Science › Hardware and Architecture › Real-Time Systems Scheduling
- Keywords
- privilege escalation, arbitrary code execution, microcontroller security, Internet of Things security
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