The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.
A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area
Abstract
This paper presents the first MRAM-based In-Memory-Computing (IMC) macro, implemented as a 128-kb array in an advanced-node 22nm FD-SOI technology. The design maximizes IMC row parallelism for energy efficiency and throughput, while addressing the critical challenges this raises, namely: high column currents; high output dynamic-range requirements; and large area of peripheral readout circuits. These are addressed through current-insensitive column-multiplexing and high-sensitivity readout circuits, occupying 26% of the macro area. Residual IMC non-idealities, arising from statistical circuit variations, are modeled and incorporated in a chip-generalized one-time neural-network training algorithm, with CIFAR-10 image-classification accuracy demonstrated at 90.1%, equal to ideal digital computation. The design addresses the particularly high sensitivity required for MRAM-based IMC compared to other non-volatile memory technologies, while achieving area-normalized throughput of 758 GOPS/mm2and energy efficiency of 5.1 TOPS/W for the macro.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
Simulations show that an analog in-memory computing design with complementary programming is considerably less robust than the authors' approach, especially at lower supply voltage.
“These simulations, where the variability of memristors is modeled based on measurements of our devices, show that the analog approach is considerably less robust than our approach, especially at lower supply voltage.”
From Powering AI at the edge: A robust, memristor-based binarized neural network with near-memory computing and miniaturized solar cell (2024) · cites this paper as [27]
Citations
Cites
Liu, Q., Gao, B., Yao, P., Wu, D., Chen, J., Pang, Y., Zhang, W., Liao, Y., Xue, C.-X., Chen, W.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9062953 · Cited by 308 · cited 2×
“While recent IMCs works have targeted ReRAM-based eNVM for row-parallel operation [1-4], IMC IP is required in the range of technologies suited for different application needs.”
BackgroundMethodXue, C.-X., Huang, T.-Y., Liu, J.-S., Chang, T.-W., Kao, H.-Y., Wang, J.-H., Liu, T.-W., Wei, S.-Y., Huang, S.-P., Wei, W.-C., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC) · doi:10.1109/isscc19947.2020.9063078 · Cited by 230 · cited 1×
“While recent IMCs works have targeted ReRAM-based eNVM for row-parallel operation [1-4], IMC IP is required in the range of technologies suited for different application needs.”
BackgroundYin, S., Sun, X., Yu, S., & Seo, J.-S. (2020) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2020.3015178 · Cited by 171 · cited 1×
“While recent IMCs works have targeted ReRAM-based eNVM for row-parallel operation [1-4], IMC IP is required in the range of technologies suited for different application needs.”
Background
Flagged first, then by citations
Cited by
Sorted by citations
Jebali, F., Majumdar, A., Turck, C., Harabi, K.-E., Faye, M.-C., Muhr, E., Walder, J.-P., Bilousov, O., Michaud, A., Vianello, E., et al. (2024) · Nature Communications · doi:10.1038/s41467-024-44766-6 · Cited by 58
Metadata
- Authors
- Deaville, P., Zhang, B., Chen, L.-Y., & Verma, N.
- Affiliations
- Princeton University (US)
- Venue
- ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
- Publisher
- IEEE
- Published
- 2021-09-13
- Pages
- 75-78
- ISSN
- 1930-8833 (ISSN-L)
- OpenAlex
- W3209341468
- Cited by
- 36
- References
- 3
- Citations by year
- 2026: 1 · 2025: 7 · 2024: 6 · 2023: 13 · 2022: 9
- FWCI
- 10.99
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- European Solid-State Circuits Conference (ESSCIRC) (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Ferroelectric and Negative Capacitance Devices
- Keywords
- MRAM, in-memory computing, neural network training, 22nm FDSOI, energy efficiency, throughput, non-volatile memory
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
