The DOI matches its Crossref record; 16 of the 16 references it cites were found in a registry or an index.
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
Abstract
Convolutional Neural Networks (ConvNets) are a powerful Deep Learning model, providing state-of-the-art accuracy to many emerging classification problems. However, ConvNet classification is a computationally heavy task, suffering from rapid complexity scaling. This paper presents fpgaConvNet, a novel domain-specific modelling framework together with an automated design methodology for the mapping of ConvNets onto reconfigurable FPGA-based platforms. By interpreting ConvNet classification as a streaming application, the proposed framework employs the Synchronous Dataflow (SDF) model of computation as its basis and proposes a set of transformations on the SDF graph that explore the performance-resource design space, while taking into account platform-specific resource constraints. A comparison with existing ConvNet FPGA works shows that the proposed fully-automated methodology yields hardware designs that improve the performance density by up to 1.62× and reach up to 90.75% of the raw performance of architectures that are hand-tuned for particular ConvNets.
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Cites
Gradient-based learning applied to document recognition
Lecun, Y., Bottou, L., Bengio, Y., & Haffner, P. (1998) · Proceedings of the IEEE · doi:10.1109/5.726791 · Cited by 58,805
Caffe: Convolutional Architecture for Fast Feature Embedding
Jia, Y., Shelhamer, E., Donahue, J., Karayev, S., Long, J., Girshick, R., Guadarrama, S., & Darrell, T. (2014) · Proceedings of the 22nd ACM international conference on Multimedia · doi:10.1145/2647868.2654889 · Cited by 11,077
Learning Deep Architectures for AI
Bengio, Y. (2009) · Foundations and Trends® in Machine Learning · doi:10.1561/2200000006 · Cited by 6,938
Learning Deep Architectures for AI
Bengio, Y. (2009) · now publishers, Inc. eBooks · doi:10.1561/9781601982957 · Cited by 4,941
Modern heuristic techniques for combinatorial problems
Reeves, C. R. (1993) · Medical Entomology and Zoology · Cited by 2,580
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158
Lee, E. A., & Messerschmitt, D. G. (1987) · Proceedings of the IEEE · doi:10.1109/proc.1987.13876 · Cited by 1,842
(2013) · Cited by 651
Max-pooling convolutional neural networks for vision-based hand gesture recognition
Nagi, J., Ducatelle, F., Di Caro, G. A., Ciresan, D., Meier, U., Giusti, A., Nagi, F., Schmidhuber, J., & Gambardella, L. M. (2011) · 2011 IEEE International Conference on Signal and Image Processing Applications (ICSIPA) · doi:10.1109/icsipa.2011.6144164 · Cited by 644
Convolutional face finder: a neural architecture for fast and robust face detection
Garcia, C., & Delakis, M. (2004) · IEEE Transactions on Pattern Analysis and Machine Intelligence · doi:10.1109/tpami.2004.97 · Cited by 547
NeuFlow: A runtime reconfigurable dataflow processor for vision
Farabet, C., Martini, B., Corda, B., Akselrod, P., Culurciello, E., & LeCun, Y. (2011) · CVPR 2011 WORKSHOPS · doi:10.1109/cvprw.2011.5981829 · Cited by 369
CNP: An FPGA-based processor for Convolutional Networks
Farabet, C., Poulet, C., Han, J. Y., & LeCun, Y. (2009) · 2009 International Conference on Field Programmable Logic and Applications · doi:10.1109/fpl.2009.5272559 · Cited by 367
Memory-centric accelerator design for Convolutional Neural Networks
Peemen, M., Setio, A. A. A., Mesman, B., & Corporaal, H. (2013) · 2013 IEEE 31st International Conference on Computer Design (ICCD) · doi:10.1109/iccd.2013.6657019 · Cited by 332
A 240 G-ops/s Mobile Coprocessor for Deep Neural Networks
Gokhale, V., Jin, J., Dundar, A., Martini, B., & Culurciello, E. (2014) · 2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops · doi:10.1109/cvprw.2014.106 · Cited by 300
Piecewise linear approximation applied to nonlinear function of a neural network
Amin, H. H., Curtis, K. M., & Hayes‐Gill, B. (1997) · IEE Proceedings - Circuits Devices and Systems · doi:10.1049/ip-cds:19971587 · Cited by 200
Accelerating real-time embedded scene labeling with convolutional networks
Cavigelli, L., Magno, M., & Benini, L. (2015) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/2744769.2744788 · Cited by 103
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Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
Wei, X., Yu, C. H., Zhang, P., Chen, Y., Wang, Y., Hu, H., Liang, Y., & Cong, J. (2017) · Proceedings of the 54th Annual Design Automation Conference 2017 · doi:10.1145/3061639.3062207 · Cited by 426
fpgaConvNet: Mapping regular and irregular convolutional neural networks on FPGAs
Venieris, S. I., & Bouganis, C.-S. (2019) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2018.2844093 · Cited by 161
Self-citationA Neural Network-Based On-device Learning Anomaly Detector for Edge Devices
Tsukada, M., Kondo, M., & Matsutani, H. (2020) · IEEE Transactions on Computers · doi:10.1109/tc.2020.2973631 · Cited by 81
MELTing Point: Mobile Evaluation of Language Transformers
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Metadata
- Authors
- Venieris, S. I., & Bouganis, C.-S.
- Venue
- 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)
- Publisher
- IEEE
- Published
- 2016-05
- Pages
- 40-47
- OpenAlex
- W2513568085
- Cited by
- 267
- References
- 16
- FWCI
- 21.85
- Type
- conference paper
- Language
- en
- Open access
- closed
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