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Cited by 43Cryptographic Implementations and SecurityCoding theory and cryptographyEmbedded Systems and FPGA Applications

The DOI matches its Crossref record; 1 of the 1 references it cites were found in a registry or an index.

Comparison of the hardware architectures and FPGA implementations of stream ciphers

Galanis, M.D., Kitsos, P., Kostopoulos, G., Sklavos, N., Koufopavlou, O., Goutis, C.E.·2005·Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.
DOI 10.1109/icecs.2004.1399745
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Abstract

In this paper, the hardware implementations of five representative stream ciphers are compared in terms of performance and consumed area. The ciphers used for the comparison are the A5/1, W7, E0, RC4 and Helix. The first three ones have been used for the security part of well-known standards. The Helix cipher is a recently introduced fast, word oriented, stream cipher. The W7 algorithm has been recently proposed as a more trustworthy solution for GSM, due to the security problems that occurred concerning the A5/1 strength. The designs were coded using the VHDL language. For the hardware implementation of the designs, an FPGA device was used. The implementation results illustrate the hardware performance of each cipher in terms of throughput-to-area ratio. This ratio equals: 5.88 for the A5/1, 1.26 for the W7, 0.21 for the E0, 2.45 for the Helix and 0.86 for the RC4.

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Research works printed but not linked: 11

  1. 0, Recommendation GSM 02.09, European Telecommunications Standards Institute (ETSI)
  2. 2001, Specification of the Bluetooth System
  3. hu, 1999, A CPLD-based RC4 cracking system, Proc IEEE Canadian Conf Electrical and Computer Engineering, 397
  4. 2000, Overview of IEEE 802.11b security, Intel Technology Journal Q2
  5. 10.1109/TIT.2002.806129 · DOI
  6. thomas, 2002, The W7 stream cipher algorithm, Internet draft
  7. ferguson, 2003, Helix: Fast encryption and authentication in a single cryptographic primitive, Proc Fast Software Encryption, 10.1007/978-3-540-39887-5_24 · DOI
  8. 10.1109/MWSCAS.2003.1562548 · DOI
  9. 10.1109/MPRV.2003.1186722 · DOI
  10. flamalainen, 2000, Hardware implementation of the improved WEP and RC4 encryption algorithms for wireless terminals, European Signal Processing Conference (EUSIPCO), 2289
  11. 2004, Xilinx Inc

Cited by

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Metadata

Authors
Galanis, M. D., Kitsos, P., Kostopoulos, G., Sklavos, N., Koufopavlou, O., & Goutis, C. E.
Affiliations
University of Patras (GR)
ORCID
Venue
Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004.
Publisher
IEEE
Published
2005-03-31
Pages
571-574
DOI
10.1109/icecs.2004.1399745
OpenAlex
W2535872946
Cited by
43
References
1
Citations by year
2023: 1 · 2022: 1 · 2020: 3 · 2019: 1 · 2018: 2 · 2017: 2 · 2016: 5 · 2015: 3 · 2014: 2 · 2013: 1 · 2012: 2
FWCI
2.85
Type
conference paper
Language
en
Open access
closed
Locations
IEEE International Conference on Electronics, Circuits and Systems (ICECS) (publishedVersion)
Topics
  • Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
  • Physical Sciences › Mathematics › Discrete Mathematics and Combinatorics › Coding theory and cryptography
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
Keywords
stream ciphers, FPGA implementation, hardware architecture, A5/1, W-7, RC4, VHDL, GSM security

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CoChat. (2026). Citation check: Comparison of the hardware architectures and FPGA implementations of stream ciphers. https://app.cochat.ai/papers/10.1109/icecs.2004.1399745
The paper
Galanis, M. D., Kitsos, P., Kostopoulos, G., Sklavos, N., Koufopavlou, O., & Goutis, C. E. (2005). Comparison of the hardware architectures and FPGA implementations of stream ciphers. Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004. https://doi.org/10.1109/icecs.2004.1399745