The DOI matches its Crossref record, with a small difference in title or year.
The power7TM processor SoC
Abstract
Introducing POWER7™ the latest member of the IBM POWER™ processor family. A 567 mm2chip implemented in 45nm SOI technology, holding eight quad threaded cores, a 32MB shared eDRAM L3, two memory controllers and high bandwidth SMP interfaces. The new out of order, shallow pipeline core with 12 execution units, multiport L1 caches and a private 256 kB L2 offers the efficiency to support 4× the number of cores within the same power envelope as its predecessor. Supporting over 4 GHz, the L1 data cache loop is kept to 2 cycles. Data from the L2 can be returned to the core at a rate of 32 B per cycle.
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Few years ago, CPUs had nearly 1B transistors; the recently announced Oracle SPARC M7 CPU will have more than 10B transistors on chip.
“Few years ago, CPUs had nearly 1B transistors [Wendel et al. 2010] while the recently announced Oracle SPARC M7 CPU will have more than 10B transistors on chip [Morgan 2014].”
From A Survey of CPU-GPU Heterogeneous Computing Techniques (2015) · cites this paper as Wendel et al. 2010
The 45nm POWER7 processor had 32MB eDRAM LLC, the 32nm POWER7+ had 80MB eDRAM LLC, and the 22nm POWER8 has 96MB eDRAM LLC.
“The 45nm POWER7 processor had 32MB eDRAM (embedded DRAM) LLC [Wendel et al. 2010], the 32nm POWER7+ processor had an 80MB eDRAM LLC [Zyuban et al. 2013], while the 22nm POWER8 processor has a 96MB eDRAM LLC [Fluhr et al. 2014].”
From A Survey of CPU-GPU Heterogeneous Computing Techniques (2015) · cites this paper as Wendel et al. 2010
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No references could be resolved yet.
Research works printed but not linked: 5
- pille, 0, A 32kB 2R/1 W L1 Data Cache in 45nm SOI Technology for the POWER7™ Processor, ISSCC 2010
- 10.1109/ISSCC.2010.5434074 · DOI
- barth, 0, A 45nm SOI Embedded Dram macro for the POWER7™ Processor 32MByte On-Chip L3 Cache, ISSCC 2010
- starke, 2009, POWER7™ Design, Hot Chips
- kalla, 2009, POWER7™, Hot Chips
Cited by
Sorted by citations
A Survey of CPU-GPU Heterogeneous Computing Techniques
Mittal, S., & Vetter, J. S. (2015) · ACM Computing Surveys · doi:10.1145/2788396 · Cited by 568
Metadata
- Authors
- Wendel, D., Kalla, R., Friedrich, J., Kahle, J., Leenstra, J., Lichtenau, C., Sinharoy, B., Starke, W., & Zyuban, V.
- Venue
- 2010 IEEE International Conference on Integrated Circuit Design and Technology
- Publisher
- IEEE
- Published
- 2010-06
- Pages
- 71-73
- Cited by
- 0
- References
- 0
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