Deep Neural Network Model and FPGA Accelerator Co-Design: Opportunities and Challenges
Abstract
With an explosive growth of various neural network algorithms, their high performance implementations on hardware platforms, such as GPUs and FPGAs, are becoming critical as well. Compared to widely used GPUs, FPGAs are considered to be harder for design and optimization even with the help of High Level Synthesis (HLS) tools. However, recent studies have shown that FPGAs can outperform GPUs in speed and power/energy efficiency; both factors are important in machine learning applications. In this paper, we will discuss a simultaneous DNN and hardware accelerator co-design method to push the DNN performance on FPGAs. We first summarize existing techniques and results along this direction, and then propose new ideas to further improve DNN development productivity and design quality. Finally we discuss the challenges we would face and propose some potential solutions.
Integrity signals
Registry
Cites
Statistics
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
FPGA do not have built-in cache structure.
“FPGA do not have built-in cache structure”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [89]
FPGA bandwidth typically is two generations older than high end GPU.
“the bandwidth typically is two generations older than high end GPU [89].”
From Embedded Intelligence on FPGA: Survey, Applications and Challenges (2021) · cites this paper as [89]
The citation lists haven’t been fetched yet
References 25 · Cited by 19
- Authors
- Hao, C., & Chen, D.
- Affiliations
- University of Illinois Urbana-Champaign (US)
- Venue
- 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)
- Publisher
- IEEE
- Published
- 2018-10
- Pages
- 1-4
- OpenAlex
- W2903601652
- Cited by
- 19
- References
- 25
- Citations by year
- 2026: 1 · 2025: 1 · 2024: 3 · 2023: 3 · 2022: 3 · 2021: 5 · 2020: 3
- FWCI
- 1.72
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- IEEE International Conference on Solid-State and Integrated Circuit Technology (publishedVersion)
- Funders
- Boeing
- Nvidia
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- deep neural network, FPGA accelerator, neural network hardware, high-level synthesis, GPU comparison, energy efficiency, machine learning hardware acceleration
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
