The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.
Scaling-up resistive synaptic arrays for neuro-inspired architecture: Challenges and prospect
Abstract
The crossbar array architecture with resistive synaptic devices is attractive for on-chip implementation of weighted sum and weight update in the neuro-inspired learning algorithms. This paper discusses the design challenges on scaling up the array size due to non-ideal device properties and array parasitics. Circuit-level mitigation strategies have been proposed to minimize the learning accuracy loss in a large array. This paper also discusses the peripheral circuits design considerations for the neuro-inspired architecture. Finally, a circuit-level macro simulator is developed to explore the design trade-offs and evaluate the overhead of the proposed mitigation strategies as well as project the scaling trend of the neuro-inspired architecture.
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Cites
Nanoscale Memristor Device as Synapse in Neuromorphic Systems
Jo, S. H., Chang, T., Ebong, I., Bhadviya, B. B., Mazumder, P., & Lu, W. (2010) · Nano Letters · doi:10.1021/nl904092h · Cited by 4,174 · cited 6×
“5 The weight update curve for Ag:a-Si resistive synaptic devices [6].”
BackgroundInfluentialTraining and operation of an integrated neuromorphic network based on metal-oxide memristors
Prezioso, M., Merrikh-Bayat, F., Hoskins, B. D., Adam, G. C., Likharev, K. K., & Strukov, D. B. (2015) · Nature · doi:10.1038/nature14441 · Cited by 3,001
Building high-level features using large scale unsupervised learning
Le, Q. V. (2013) · 2013 IEEE International Conference on Acoustics, Speech and Signal Processing · doi:10.1109/icassp.2013.6639343 · Cited by 1,695
Cited by
The future of electronics based on memristive systems
Zidan, M. A., Strachan, J. P., & Lu, W. D. (2018) · Nature Electronics · doi:10.1038/s41928-017-0006-8 · Cited by 2,138
Neuro-Inspired Computing With Emerging Nonvolatile Memorys
Yu, S. (2018) · Proceedings of the IEEE · doi:10.1109/jproc.2018.2790840 · Cited by 1,170
Self-citationEquivalent-accuracy accelerated neural-network training using analogue memory
Ambrogio, S., Narayanan, P., Tsai, H., Shelby, R. M., Boybat, I., di Nolfo, C., Sidler, S., Giordano, M., Bodini, M., Farinha, N. C. P., et al. (2018) · Nature · doi:10.1038/s41586-018-0180-5 · Cited by 1,151
Memristor‐Based Analog Computation and Neural Network Classification with a Dot Product Engine
Hu, M., Graves, C. E., Li, C., Li, Y., Ge, N., Montgomery, E., Davila, N., Jiang, H., Williams, R. S., Yang, J. J., et al. (2018) · Advanced Materials · doi:10.1002/adma.201705914 · Cited by 751
Choi, S., Tan, S. H., Li, Z., Kim, Y., Choi, C., Chen, P.-Y., Yeon, H., Yu, S., & Kim, J. (2018) · Nature Materials · doi:10.1038/s41563-017-0001-5 · Cited by 690
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Metadata
- Authors
- Yu, S., Chen, P.-Y., Cao, Y., Xia, L., Wang, Y., & Wu, H.
- Venue
- 2015 IEEE International Electron Devices Meeting (IEDM)
- Publisher
- IEEE
- Published
- 2015-12
- Pages
- 17.3.1-17.3.4
- ISSN
- 0163-1918 (ISSN-L)
- OpenAlex
- W2288519604
- Cited by
- 219
- References
- 3
- FWCI
- 31.88
- Type
- conference paper
- Language
- en
- Open access
- closed
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