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SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor
Abstract
SpiNNaker is a novel chip - based on the ARM processor - which is designed to support large scale spiking neural networks simulations. In this paper we describe some of the features that permit SpiNNaker chips to be connected together to form scalable massively-parallel systems. Our eventual goal is to be able to simulate neural networks consisting of 109neurons running in dasiareal timepsila, by which we mean that a similarly sized collection of biological neurons would run at the same speed. In this paper we describe the methods by which neural networks are mapped onto the system, and how features designed into the chip are to be exploited in practice. We will also describe the modelling and verification activities by which we hope to ensure that, when the chip is delivered, it will work as anticipated.
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Citations
Cites
Simple model of spiking neurons
Izhikevich, E. M. (2003) · IEEE Transactions on Neural Networks · doi:10.1109/tnn.2003.820440 · Cited by 4,828
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Face classification using electronic synapses
Yao, P., Wu, H., Gao, B., Eryilmaz, S. B., Huang, X., Zhang, W., Zhang, Q., Deng, N., Shi, L., Wong, H.-S. P., et al. (2017) · Nature Communications · doi:10.1038/ncomms15199 · Cited by 909
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Park, J., Yu, T., Joshi, S., Maier, C., & Cauwenberghs, G. (2017) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2016.2572164 · Cited by 118
Metadata
- Authors
- Khan, M. M., Lester, D. R., Plana, L. A., Rast, A., Jin, X., Painkras, E., & Furber, S. B.
- Venue
- 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence)
- Publisher
- IEEE
- Published
- 2008-06
- Pages
- 2849-2856
- OpenAlex
- W2121458485
- Cited by
- 270
- References
- 1
- FWCI
- 9.84
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Khan, M. M., Lester, D. R., Plana, L. A., Rast, A., Jin, X., Painkras, E., & Furber, S. B. (2008). SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence). https://doi.org/10.1109/ijcnn.2008.4634199
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