Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning
Abstract
Although Transformer-based language representations achieve state-of-the-art accuracy on various natural language processing (NLP) tasks, the large model size has been challenging the resource constrained computing platforms. Weight pruning, as a popular and effective technique in reducing the number of weight parameters and accelerating the Transformer, has been investigated on GPUs. However, the Transformer acceleration using weight pruning on field-programmable gate array (FPGAs) remains unexplored. This paper investigates the column balanced block-wise pruning on Transformer and designs an FPGA acceleration engine to customize the balanced blockwise matrix multiplication. We implement the Transformer model with proper hardware scheduling, and the experiments show that the Transformer inference on FPGA achieves 10.35 ms latency with the batch size of 32, which is 10.96 * speed up comparing to CPU platform and 2.08 * speed up comparing to GPU platform.
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The CBBWP storage format needs only one index pointer for every block, saving memory.
“It needs only one index pointer for every block, saving memory.”
From A Survey of Techniques for Optimizing Transformer Inference (2023) · cites this paper as [124]
CBBWP enables parallelism within and across blocks.
“CBBWP enables parallelism within and across the blocks.”
From A Survey of Techniques for Optimizing Transformer Inference (2023) · cites this paper as [124]
Cites
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An Image is Worth 16x16 Words: Transformers for Image Recognition at Scale
Dosovitskiy, A., Beyer, L., Kolesnikov, A., Weissenborn, D., Zhai, X., Unterthiner, T., Dehghani, M., Minderer, M., Heigold, G., Gelly, S., et al. (2020) · arXiv · doi:10.48550/arxiv.2010.11929 · Cited by 21,793 · see citing works
End-to-End Object Detection with Transformers
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RoBERTa: A Robustly Optimized BERT Pretraining Approach
Liu, Y., Ott, M., Goyal, N., Du, J., Joshi, M., Chen, D., Levy, O., Lewis, M., Zettlemoyer, L., & Stoyanov, V. (2019) · arXiv · doi:10.48550/arxiv.1907.11692 · Cited by 16,515 · see citing works
DistilBERT, a distilled version of BERT: smaller, faster, cheaper and lighter
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FTRANS: energy-efficient acceleration of transformers using FPGA
Li, B., Pandey, S., Fang, H., Lyv, Y., Li, J., Chen, J., Xie, M., Wan, L., Liu, H., & Ding, C. (2020) · Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design · doi:10.1145/3370748.3406567 · Cited by 206 · see citing works
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A Survey of Techniques for Optimizing Transformer Inference
Chitty-Venkata, K. T., Mittal, S., Emani, M., Vishwanath, V., & Somani, A. K. (2023) · Journal of Systems Architecture · doi:10.1016/j.sysarc.2023.102990 · Cited by 154 · see citing works
- Authors
- Peng, H., Huang, S., Geng, T., Li, A., Jiang, W., Liu, H., Wang, S., & Ding, C.
- Affiliations
- University of Connecticut (US)
- Pacific Northwest National Laboratory (US)
- University of Notre Dame (US)
- Stevens Institute of Technology (US)
- Venue
- 2021 22nd International Symposium on Quality Electronic Design (ISQED)
- Publisher
- IEEE
- Published
- 2021-04-07
- Pages
- 142-148
- OpenAlex
- W3162542754
- Cited by
- 105
- References
- 6
- Citations by year
- 2026: 6 · 2025: 20 · 2024: 32 · 2023: 24 · 2022: 19 · 2021: 4
- FWCI
- 6.46
- Type
- conference paper
- Language
- en
- Open access
- closed
- Licence
- Locations
- International Symposium on Quality Electronic Design (ISQED) (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
- Keywords
- transformer models, FPGA acceleration, weight pruning, hardware scheduling, inference latency, resource-constrained computing
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