The DOI matches its Crossref record.
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth
Abstract
The 12-core 649mm2POWER8™ leverages IBM's 22nm eDRAM SOI technology [1], and microarchitectural enhancements to deliver up to 2.5× the socket performance [2] of its 32nm predecessor, POWER7+™ [3]. POWER8 contains 4.2B transistors and 31.5μF of deep-trench decoupling capacitance. Three thin-oxide transistor Vts are used for power/performance tuning, and thick-oxide transistors enable high-voltage I/O and analog designs. The 15-layer BEOL contains 5–80nm, 2–144nm, 3–288nm, and 3–640nm pitch layers for low-latency communication as well as 2–2400nm ultra-thick-metal (UTM) pitch layers for low-resistance distribution of power and clocks.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
Recent CPUs have 8 to 32 cores; CPUs with more than 60 cores are likely to be available in the near future.
“Earlier CPUs had only one or two cores, while as recent CPUs have 8 to 32 cores [Fluhr et al. 2014;Morgan 2014] and CPUs with more than 60 cores are likely to be available in near future [Gardner 2014].”
From A Survey of CPU-GPU Heterogeneous Computing Techniques (2015) · cites this paper as Fluhr et al. 2014
The 45nm POWER7 processor had 32MB eDRAM LLC, the 32nm POWER7+ had 80MB eDRAM LLC, and the 22nm POWER8 has 96MB eDRAM LLC.
“The 45nm POWER7 processor had 32MB eDRAM (embedded DRAM) LLC [Wendel et al. 2010], the 32nm POWER7+ processor had an 80MB eDRAM LLC [Zyuban et al. 2013], while the 22nm POWER8 processor has a 96MB eDRAM LLC [Fluhr et al. 2014].”
From A Survey of CPU-GPU Heterogeneous Computing Techniques (2015) · cites this paper as Fluhr et al. 2014
Citations
Cites
No references could be resolved yet.
Cited by
Sorted by citations
A Survey of CPU-GPU Heterogeneous Computing Techniques
Mittal, S., & Vetter, J. S. (2015) · ACM Computing Surveys · doi:10.1145/2788396 · Cited by 568
Metadata
- Authors
- Fluhr, E. J., Friedrich, J., Dreps, D., Zyuban, V., Still, G., Gonzalez, C., Hall, A., Hogenmiller, D., Malgioglio, F., Nett, R., Paredes, J., Pille, J., Plass, D., Puri, R., Restle, P., Shan, D., Stawiasz, K., Deniz, Z. T., Wendel, D., & Ziegler, M.
- Venue
- 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
- Publisher
- IEEE
- Published
- 2014-02
- Pages
- 96-97
- Cited by
- 26
- References
- 0
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
