Speed record of AES-CTR and AES-ECB bit-sliced implementation on GPUs
Abstract
The advanced encryption standard (AES) has been widely used to protect digital data in various applications, such as secure IoT communication, files encryption, and pseudorandom number generation. The efficient implementation of AES on parallel architecture, such as graphics processing unit (GPU), has attracted considerable interest over the past decade. These prior studies mainly implemented the AES electronics code book (ECB) and counter (CTR) mode using the table-based approach. In this brief, we set a new speed record of AES-ECB and AES-CTR on GPU based on the proposed bit-sliced implementation techniques. Our implementation achieved 2.6% (ECB) and 9% (CTR) faster than the state-of-the-art table-based implementation on a RTX3080 GPU. Our work evaluated on an embedded GPU (Jetson Orin Nano) can also achieve high throughput at 60 Gb/s, which is 1.9% (ECB) and 7% (CTR) faster than state-of-the-art.
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Building upon the high-performance bit-sliced AES-CTR core architecture described by Lee et al. (2024), we introduced a critical modification to ensure cryptographic interoperability across heterogeneous hardware.
“Building upon the high-performance bit-sliced AESCTR core architecture described by Lee et al. (2024), we introduced a critical modification to ensure cryptographic interoperability across heterogeneous hardware.”
From A high-throughput AES-GCM implementation on GPUs for secure, policy-based access to massive astronomical catalogs (2026) · cites this paper as Lee et al. (2024)
The original algorithm's counter generation logic was coupled to the GPU grid geometry (total thread count), causing the keystream to vary with hardware configuration.
“The original algorithm's counter generation logic was coupled to the GPU grid geometry (total thread count), causing the keystream to vary with hardware configuration.”
From A high-throughput AES-GCM implementation on GPUs for secure, policy-based access to massive astronomical catalogs (2026) · cites this paper as Lee et al. (2024)
This is also the choice made by Lee et al. (2024) and Lee et al. (2025), whose implementation we adopt as our cryptographic core.
“This is also the choice made by Lee et al. (2024) and Lee et al. (2025), whose implementation we adopt as our cryptographic core.”
From A high-throughput AES-GCM implementation on GPUs for secure, policy-based access to massive astronomical catalogs (2026) · cites this paper as Lee et al. (2024)
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Lemes-Perera, S., R. Alarcon, M., Caballero-Gil, P., & Serra-Ricart, M. (2026) · Astronomy and Computing · doi:10.1016/j.ascom.2026.101153 · Cited by 1 · see citing works
- Authors
- Lee, W.-K., Seo, S. C., Seo, H., Kim, D. C., & Hwang, S. O.
- Affiliations
- Universiti Tunku Abdul Rahman (MY)
- Kookmin University (KR)
- Hansung University (KR)
- Department of Financial Information Security, Kookmin University, Seoul, South Korea
- Gachon University (KR)
- Venue
- IEEE Embedded Systems Letters
- Published
- 2024-12
- Volume
- 16
- Issue
- 4
- Pages
- 481-484
- ISSN
- 1943-0663 (ISSN-L)
- 1943-0671
- OpenAlex
- W4399452422
- Cited by
- 4
- References
- 0
- Citations by year
- 2026: 3 · 2025: 1
- FWCI
- 0.59
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Embedded Systems Letters (publishedVersion)
- Funders
- National Research Foundation of Korea (2019H1D3A1A01102607)
- Gachon University research fund (GCU-202304050001)
- Topics
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Computer Science › Information Systems › Cryptography and Residue Arithmetic
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Keywords
- AES, AES-CTR, GPU acceleration, encryption throughput, Jetson Orin Nano, embedded GPU, speed records
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