The DOI matches its Crossref record; 16 of the 16 references it cites were found in a registry or an index.
ANUBIS: Hybrid FPAA-FPGA Architecture for Entropy-Based True Random Number Generation in Secure UAV Communication
Abstract
Field-programmable gate arrays (FPGAs) and field-programmable analog arrays (FPAAs) are reconfigurable circuits that enable flexible digital and analog implementations post-manufacturing. FPGAs are widely used in telecommunications, mixed-signal, and embedded systems due to their parallel processing and reconfigurability. Meanwhile, FPAAs provide flexibility for analog systems, which is crucial for modern mixed-signal processing. This letter introduces ANUBIS, a hybrid system combining FPGA and FPAA technologies to generate true random number generators (TRNGs) for secure UAV communication. Due to its reliability and cost efficiency, ANUBIS leverages a thermistor circuit as an entropy source. The FPAA amplifies the analog noise generated by the thermistor, while the FPGA digitizes and processes the signal using Von Neumann whitening (VNW) to remove bias. The ASCON hash function is applied to the whitened bitstream to generate cryptographically secure keys. These keys are utilized in a DHKE to enable secure communication via Bluetooth low energy (BLE), an ideal protocol for energy-constrained UAV applications. ANUBIS demonstrates reconfigurability, power efficiency, and ease of implementation, showcasing its potential for secure communication applications. It achieves robust randomization, setting a new standard for UAV communication security and addressing applications requiring reliable TRNG solutions. The system consumes 1.615 W in total, with 1.54 W consumed by the FPGA and 75 mW by the FPAA. Resource utilization on the PYNQ-Z1 board includes 5186 LUTs (9.75%), 549 units of memory (3.15%), and 5.5 units of BRAM (3.93%), indicating moderate resource usage with room for future enhancements. By integrating reliable analog noise harvesting with efficient digital post-processing, ANUBIS offers a novel approach to TRNG design, demonstrating the potential for broader cryptographic applications in resource-constrained environments.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
In the citing paper
“We used the composite field arithmetic method proposed by [2] for efficient S-box computation.”
From First Fully Pipelined High Throughput FPGA Implementation and GPU Optimization of Wider Variant of AES (2026) · cites this paper as [2]
Citations
Cites
FPGA-Based High-Performance Parallel Architecture for Homomorphic Computing on Encrypted Data
Roy, S. S., Turan, F., Jarvinen, K. U., Vercauteren, F., & Verbauwhede, I. M. R. (2019) · IEEE International Symposium on High-Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2019.00052 · Cited by 195
Khan, M. A., Qureshi, I. M., & Khanzada, F. (2019) · Drones · doi:10.3390/drones3010016 · Cited by 139
True Random Number Generators Using Electrical Noise
Gong, L., Zhang, J., Liu, H., Sang, L., & Wang, Y. (2019) · IEEE Access · doi:10.1109/access.2019.2939027 · Cited by 77 · cited 1×
“TRNGs [8] emerged to address these issues by generating randomness from physical processes, enhancing security.”
Kareem, H., & Dunaev, D. (2021) · International Conference on Circuits, Systems and Simulation (ICCSS) · doi:10.1109/iccss51193.2021.9464217 · Cited by 39
RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT
Wei, X., El-Hadedy, M., Mosanu, S., et al. (2022) · IEEE International System-on-Chip Conference (SOCC) · doi:10.1109/socc56010.2022.9908100 · Cited by 34
Self-citationA dynamic partial reconfigurable overlay concept for PYNQ
Jansen, B., Zimprich, P., & Hübner, M. (2017) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.23919/fpl.2017.8056786 · Cited by 30
Random Number Generator Using Sensors for Drone
Cho, S.-M., Hong, E., & Seo, S.-H. (2020) · IEEE Access · doi:10.1109/access.2020.2972958 · Cited by 27
A true random number generator that utilizes thermal noise in a programmable system‐on‐chip (PSoC)
Matsuoka, S., Ichikawa, S., & Fujieda, N. (2021) · International Journal of Circuit Theory and Applications · doi:10.1002/cta.3046 · Cited by 25
Hasler, J. (2022) · Custom Integrated Circuits Conference · doi:10.1109/cicc53496.2022.9772732 · Cited by 15
True Random Number Generator (TRNG) for Secure Communications in the Era of IoT
Ji, Z., Brown, J., & Zhang, J. (2020) · China Semiconductor Technology International Conference (CSTIC) · doi:10.1109/cstic49141.2020.9282535 · Cited by 14
Research works printed but not linked: 3
- von Neumann, 1951, Various techniques used in connection with random digits, Nat. Bureau Stand., 12, 5
- Knuth, 1997, The Art of Computer Programming, Volume 2: Seminumerical Algorithms
- Grujić, INVITED: Design principles for true random number generators for security applications, 1
Cited by
Sorted by citations
Malal, A., & Tezcan, C. (2026) · Journal of Cryptographic Engineering · doi:10.1007/s13389-025-00388-2 · Cited by 4
“For instance, El-0123456789 Hadedy et al. proposed ANUBIS, a hybrid FPGA design for true random number generation [2].”
Metadata
- Authors
- El-Hadedy, M., Abelian, A., Lee, K., Cheng, B. N., & Hwu, W.-M.
- Affiliations
- California State Polytechnic University (US)
- Naval Surface Warfare Center (US)
- University of Illinois Urbana-Champaign (US)
- Venue
- IEEE Embedded Systems Letters
- Published
- 2025-06
- Volume
- 17
- Issue
- 3
- Pages
- 164-167
- ISSN
- 1943-0663 (ISSN-L)
- 1943-0671
- OpenAlex
- W4405179800
- Cited by
- 7
- References
- 16
- Citations by year
- 2026: 2 · 2025: 5
- FWCI
- 2.18
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Embedded Systems Letters (publishedVersion)
- Funders
- U.S. Navy Naval Engineering Education Consortium (N001742310002)
- Office of Naval Research (ONR) Summer Faculty Research Program
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Physical Unclonable Functions (PUFs) and Hardware Security
- Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- true random number generation, field programmable analog array, FPGA, entropy source, Diffie-Hellman key exchange, Bluetooth Low Energy, UAV communication security, hardware-based cryptography, energy-constrained devices, reconfigurable hardware
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
