The DOI matches its Crossref record; 6 of the 6 references it cites were found in a registry or an index.
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
Abstract
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cores representing different points in the power/performance design space; during an application's execution, system software dynamically chooses the most appropriate core to meet specific performance and power requirements. Our evaluation of this architecture shows significant energy benefits. For an objective function that optimizes for energy efficiency with a tight performance threshold, for 14 SPEC benchmarks, our results indicate a 39% average energy reduction while only sacrificing 3% in performance. An objective function that optimizes for energy-delay with looser performance bounds achieves, on average, nearly a factor of three improvements in energy-delay product while sacrificing only 22% in performance. Energy savings are substantially more than chip-wide voltage/frequency scaling.
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Cites
Automatically characterizing large scale program behavior
Sherwood, T., Perelman, E., Hamerly, G., & Calder, B. (2002) · Proceedings of the 10th international conference on Architectural support for programming languages and operating systems · doi:10.1145/605397.605403 · Cited by 1,674
Wattch: a framework for architectural-level power analysis and optimizations
Brooks, D. M., Tiwari, V., & Martonosi, M. (2002) · doi:10.1109/isca.2000.854380 · Cited by 1,122
Comparing algorithm for dynamic speed-setting of a low-power CPU
Govil, K., Chan, E., & Wasserman, H. (1995) · Proceedings of the 1st annual international conference on Mobile computing and networking - MobiCom '95 · doi:10.1145/215530.215546 · Cited by 454
Semeraro, G., Magklis, G., Balasubramonian, R., Albonesi, D. H., Dwarkadas, S., & Scott, M. L. (2004) · Proceedings Eighth International Symposium on High Performance Computer Architecture · doi:10.1109/hpca.2002.995696 · Cited by 368
Run-time power estimation in high performance microprocessors
Joseph, R., & Martonosi, M. (2002) · International Symposium on Low Power Electronics and Design (ISLPED) · doi:10.1109/lpe.2001.945389 · Cited by 78
Unified architecture level energy-efficiency metric
Zyuban, V. V. (2002) · ACM Great Lakes Symposium on VLSI (GLSVLSI) · doi:10.1145/505306.505313 · Cited by 18
Cited by
Amdahl's Law in the Multicore Era
Hill, M. D., & Marty, M. R. (2008) · Computer · doi:10.1109/mc.2008.209 · Cited by 1,262
Optimizing energy consumption for data centers
Rong, H., Zhang, H., Xiao, S., Li, C., & Hu, C. (2016) · Renewable and Sustainable Energy Reviews · doi:10.1016/j.rser.2015.12.283 · Cited by 398
Splitwise: Efficient Generative LLM Inference Using Phase Splitting
Patel, P., Choukse, E., Zhang, C., Shah, A., Goiri, Í., Maleki, S., & Bianchini, R. (2024) · 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca59077.2024.00019 · Cited by 298
“Research on heterogeneous multiprocessor CPU scheduling attempts to match workload heterogeneity to hardware heterogeneity [29], [40], [41], [50], [76], [80].”
Background
Metadata
- Authors
- Kumar, R., Farkas, K. I., Jouppi, N. P., Ranganathan, P., & Tullsen, D. M.
- Venue
- 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449)
- Publisher
- IEEE Comput. Soc
- Published
- 2003-01-01
- Pages
- 81-92
- ISSN
- 1072-4451 (ISSN-L)
- OpenAlex
- W4250692521
- Cited by
- 373
- References
- 6
- FWCI
- 6.70
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Kumar, R., Farkas, K. I., Jouppi, N. P., Ranganathan, P., & Tullsen, D. M. (2004). Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction. 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449). https://doi.org/10.1109/micro.2003.1253185
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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