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AI and Memory Wall
Open accessAbstract
The availability of unprecedented unsupervised training data, along with neural scaling laws, has resulted in an unprecedented surge in model size and compute requirements for serving/training LLMs. However, the main performance bottleneck is increasingly shifting to memory bandwidth. Over the past 20 years, peak server hardware FLOPS has been scaling at 3.0×/2yrs, outpacing the growth of DRAM and interconnect bandwidth, which have only scaled at 1.6 and 1.4 times every 2 years, respectively. This disparity has made memory, rather than compute, the primary bottleneck in AI applications, particularly in serving. Here, we analyze encoder and decoder Transformer models and show how memory bandwidth can become the dominant bottleneck for decoder models. We argue for a redesign in model architecture, training, and deployment strategies to overcome this memory limitation.
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“These observations are consistent with Gholami et al.'s (2024) findings on AI's restricted memory capacity and its tendency to produce narrative incoherence in longer texts.”
From How Creative Is AI Writing? Generative and Collaborative AI in Japanese Fiction (2026) · cites this paper as Gholami et al.'s (2024)
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In the citing paper
“the relative weakness of zero-shot generation is consistent with research on AI's limitations in sustaining narrative coherence (Gholami et al., 2024)”
From How Creative Is AI Writing? Generative and Collaborative AI in Japanese Fiction (2026) · cites this paper as Gholami et al., 2024
Experimental — accuracy not yet measuredThe check wasn’t confident either way, so it gives no verdict — never disputed.
In the citing paper
“Gholami et al. (2024) identify restricted memory capacity as one of the primary challenges of AI-assisted fiction writing: as a story progresses, the model tends to lose track of earlier plot points and character details, which result in narrative inconsistencies.”
From How Creative Is AI Writing? Generative and Collaborative AI in Japanese Fiction (2026) · cites this paper as Gholami et al. (2024)
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“Every additional factor between these curves has to be absorbed by off chip traffic, gradient rematerialization, or model partitioning, each of which exacts an energy and latency tax that is already dominant in production data centers [2].”
POLARON: Precision-Aware On-device Learning and Adaptive Runtime-Configurable AI Acceleration
Lokhande, M., Jain, A., & Vishvakarma, S. K. (2026) · Communications in computer and information science · doi:10.1007/978-3-032-26305-6_26
“This progress has accelerated the adoption of AI on mobile and Internet of Things (IoT) platforms, where stringent power, memory, and bandwidth constraints [3], [4] pose significant challenges for real-time inference and on-device learning as visible from Fig.”
Fundamentals and applications of altermagnetism
Han, S., Lee, H.-W., Kang, C., Rhim, S. H., Ok, J. M., Kim, C., Lee, J. S., Sohn, B., Ko, H.-W., Sohn, C., et al. (2026) · Journal of the Korean Physical Society · doi:10.1007/s40042-026-01731-4
CtxMem: OS-Hardware Co-designed Tiered Memory with DRAM-SSD Hybrid CXL Devices
Longyi, Z., Zhong, K., He, H., Tan, Z., & Liu, D. (2026) · ACM/IEEE Design Automation Conference (DAC) · doi:10.1145/3770743.3804082
Gu, J., Chen, W., Yu, H., & Xu, J. (2026) · IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) · doi:10.1109/edssc70455.2026.11736493
“However, the exponential growth in model parameters has far outpaced the scaling of hardware computing power, imposing significant bandwidth and compute challenges for resource-constrained deployments [2].”
GPU Memory Bandwidth and the MemoryWall on Computing Performance
Ye, T. (2026) · Science and Technology of Engineering Chemistry and Environmental Protection · doi:10.61173/stecep16262
Metadata
- Authors
- Gholami, A., Yao, Z., Kim, S., Hooper, C., Mahoney, M. W., & Keutzer, K.
- Affiliations
- International Computer Science Institute (US)
- Snowflake Inc. (United States) (US)
- University of California, Berkeley (US)
- Venue
- IEEE Micro
- Published
- 2024-05
- Volume
- 44
- Issue
- 3
- Pages
- 33-39
- ISSN
- 0272-1732 (ISSN-L)
- 1937-4143
- OpenAlex
- W4393145114
- Cited by
- 369
- References
- 13
- Citations by year
- 2026: 143 · 2025: 166 · 2024: 47
- FWCI
- 110.55
- Type
- journal article
- Language
- en
- Open access
- green
- arxiv.org
- Licence
- Locations
- IEEE Micro (publishedVersion)
- arXiv (Cornell University) (submittedVersion, cc-by)
- KAIST Institutional Repository (KAIST) (submittedVersion)
- arXiv (Cornell University) (cc-by)
- Funders
- National Science Foundation
- U.S. Department of Energy
- Intel Corporation
- Samsung Advanced Institute of Technology
- Korea Foundation for Advanced Studies
- Samsung
- Office of Naval Research
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Artificial Intelligence › Topic Modeling
- Keywords
- memory wall, memory bandwidth, large language models, transformer models, DRAM scaling, interconnect bandwidth, model serving
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
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