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Cited by 505

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A Procedure for Placement of Standard-Cell VLSI Circuits

Dunlop, A.E., Kernighan, B.W.·1985·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Abstract

This paper describes a method of automatic placement for standard cells (polycells) that yields areas within 10-20 percent of careful hand placements. The method is based on graph partitioning to identify groups of modules that ought to be close to each other, and a technique for properly accounting for external connections at each level of partitioning. The placement procedure is in production use as part of an automated design system; it has been used in the design of more than 40 chips, in CMOS, NMOS, and bipolar technologies.

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Metadata

Authors
Dunlop, A. E., & Kernighan, B. W.
Venue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Published
1985-01
Volume
4
Issue
1
Pages
92-98
ISSN
0278-0070 (ISSN-L)
OpenAlex
W1980746862
Cited by
505
References
0
FWCI
15.62
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: A Procedure for Placement of Standard-Cell VLSI Circuits. https://app.cochat.ai/papers/10.1109/tcad.1985.1270101
The paper
Dunlop, A. E., & Kernighan, B. W. (1985). A Procedure for Placement of Standard-Cell VLSI Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/tcad.1985.1270101

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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).

Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.