The DOI matches its Crossref record; 12 of the 12 references it cites were found in a registry or an index.
A Survey and Evaluation of FPGA High-Level Synthesis Tools
Open accessAbstract
High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits, where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia. All these tools may have different input languages, perform different internal optimizations, and produce results of different quality, even for the very same input description. Hence, it is challenging to compare their performance and understand which is the best for the hardware to be implemented. We present a comprehensive analysis of recent HLS tools, as well as overview the areas of active interest in the HLS research community. We also present a first-published methodology to evaluate different HLS tools. We use our methodology to compare one commercial and three academic tools on a common set ofCbenchmarks, aiming at performing an in-depth evaluation in terms of performance and the use of resources.
Overview
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
The claims and statistics of this paper haven’t been checked yet.
Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.
Self-check
Percentages, sums and reported differences re-computed from the paper’s own numbers.
The self-check needs the paper’s full text.
Citations
Cites
LLVM: A compilation framework for lifelong program analysis & transformation
Lattner, C., & Adve, V. (2004) · International Symposium on Code Generation and Optimization, 2004. CGO 2004. · doi:10.1109/cgo.2004.1281665 · Cited by 2,681
Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158
Borkar, S., & Chien, A. A. (2011) · Communications of the ACM · doi:10.1145/1941487.1941507 · Cited by 966
High-Level Synthesis for FPGAs: From Prototyping to Deployment
Cong, J., Liu, B., Neuendorffer, S., Noguera, J., Vissers, K., & Zhang, Z. (2011) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2011.2110592 · Cited by 846
A reconfigurable fabric for accelerating large-scale datacenter services
Putnam, A., Caulfield, A. M., Chung, E. S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G. P., Gray, J., et al. (2014) · ACM SIGARCH Computer Architecture News · doi:10.1145/2678373.2665678 · Cited by 693
A reconfigurable fabric for accelerating large-scale datacenter services
Putnam, A., Caulfield, A. M., Chung, E. S., Chiou, D., Constantinides, K., Demme, J., Esmaeilzadeh, H., Fowers, J., Gopal, G. P., Gray, J., et al. (2014) · 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA) · doi:10.1109/isca.2014.6853195 · Cited by 576
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Canis, A., Choi, J., Aldham, M., Zhang, V., Kammoona, A., Anderson, J. H., Brown, S., & Czajkowski, T. (2011) · Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays · doi:10.1145/1950413.1950423 · Cited by 531
Self-citationCoussy, P., & Morawiec, A. (2008) · Springer eBooks · doi:10.1007/978-1-4020-8588-8 · Cited by 402
The Garp architecture and C compiler
Callahan, T. J., Hauser, J. R., & Wawrzynek, J. (2000) · Computer · doi:10.1109/2.839323 · Cited by 392
Designing Custom Arithmetic Data Paths with FloPoCo
de Dinechin, F., & Pasca, B. (2011) · IEEE Design & Test of Computers · doi:10.1109/mdt.2011.44 · Cited by 336
Cited by
Real-Time Underwater Image Recognition with FPGA Embedded System for Convolutional Neural Network
Zhao, M., Hu, C., Wei, F., Wang, K., Wang, C., & Jiang, Y. (2019) · Sensors · doi:10.3390/s19020350 · Cited by 55
Metadata
- Authors
- Nane, R., Sima, V.-M., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, Y. T., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J., & Bertels, K.
- Venue
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Published
- 2016-10
- Volume
- 35
- Issue
- 10
- Pages
- 1591-1604
- ISSN
- 0278-0070 (ISSN-L)
- 1937-4151
- OpenAlex
- W2343695530
- Cited by
- 532
- References
- 12
- FWCI
- 67.30
- Type
- journal article
- Language
- en
- Open access
- green
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
How to cite
Cite CoChat for the checks on this page, and the paper for its own findings.
- This page
- CoChat. (2026). Citation check: A Survey and Evaluation of FPGA High-Level Synthesis Tools. https://app.cochat.ai/papers/10.1109/tcad.2015.2513673
- The paper
- Nane, R., Sima, V.-M., Pilato, C., Choi, J., Fort, B., Canis, A., Chen, Y. T., Hsiao, H., Brown, S., Ferrandi, F., Anderson, J., & Bertels, K. (2016). A Survey and Evaluation of FPGA High-Level Synthesis Tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. https://doi.org/10.1109/tcad.2015.2513673
Data sources
Bibliographic data: Semantic Scholar, OpenAlex, Crossref.
Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
Semantic Scholar’s data is described in: Kinney, R., et al. (2023). The Semantic Scholar Open Data Platform. arXiv:2301.10140.
