Cited by 7183D IC and TSV technologiesElectronic Packaging and Soldering TechnologiesInterconnection Networks and Systems

Recent Advances and Trends in Advanced Packaging

Lau, John H.·2022·IEEE Transactions on Components, Packaging and Manufacturing Technology

Abstract

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

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Crossref · 10.1109/tcpmt.2022.3144461

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  • Advanced packaging techniques such as TSV, TSV-less interposers, and heterogeneous integration are used to improve signal integrity, power and thermal distribution, and die yield by breaking complex and large SoCs into smaller chiplets.

    “More advanced packaging techniques (see Fig. 4) such as through-silicon via (TSV), TSV-less interposers, and heterogeneous integration are used to improve signal integrity, power and thermal distribution, and die yield by breaking complex and large SoCs into smaller chiplets126.”

    From Roadmapping the next generation of silicon photonics (2024) · cites this paper as [126]

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Authors
Lau, J. H.
Affiliations
Unimicron Technology Corporation, Taoyuan, Taiwan
Corresponding author
Lau, John H.
Venue
IEEE Transactions on Components, Packaging and Manufacturing Technology
Published
2022-02
Volume
12
Issue
2
Pages
228-252
ISSN
  • 2156-3950 (ISSN-L)
  • 2156-3985
OpenAlex
W4206364646
Cited by
718
References
0
Citations by year
2026: 210 · 2025: 242 · 2024: 141 · 2023: 98 · 2022: 24 · 2021: 1 · 2019: 1 · 2018: 1
FWCI
34.58
Type
journal article
Language
en
Open access
closed
Locations
IEEE Transactions on Components Packaging and Manufacturing Technology (publishedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › 3D IC and TSV technologies
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Electronic Packaging and Soldering Technologies
  • Physical Sciences › Computer Science › Computer Networks and Communications › Interconnection Networks and Systems
Keywords
advanced packaging, chiplets, heterogeneous integration, silicon bridge, fan-out packaging, wafer level chip scale package, low-loss dielectrics, flip-chip bonding, thermocompression bonding, hybrid bonding, interconnect density, substrate design

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