An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge
Abstract
Transformer-like network has shown remarkable high performance in both natural language processing and computer vision. However, the huge computational demands in non-linear floating-point arithmetic and the irregular memory access requirement in self-attention mechanism make it still a challenge to deploy Transformer on edge. To address the above issues, we propose integer-only quantization scheme for the simplification of non-linear operations (such as LayerNorm, Softmax and Gelu), meanwhile algorithm-hardware co-design strategy is applied to guarantee both the high accuracy and high efficiency. Besides, we construct general-purpose group vector systolic array to efficiently accelerate the matrix multiplication operations including both regular matrix-multiplication/convolution and the irregular multi-head self-attention mechanism. Unified data-package strategy and flexible on-/off-chip data storage management strategy are also proposed to further improve the performance. The design has been deployed on Xilinx ZCU102 FPGA platform, achieving an overall inference latency of 4.077ms and 11.15ms per image for ViT-tiny and ViT-s, respectively. The average throughput can reach as high as 762.7 GOPs, which shows significant improvement over the previous state-of-the-art FPGA Transformer accelerator.
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Huang et al. use a versatile group vector systolic array optimized for matrix multiplication.
“A critical element of their approach is the versatile group vector systolic array, optimized for the efficient execution of matrix multiplication tasks.”
From Model Quantization and Hardware Acceleration for Vision Transformers: A Comprehensive Survey (2024) · cites this paper as [22]
Huang et al. employ a unified strategy for packaging data and dynamic on-/off-chip data storage management.
“Additionally, the framework employs a unified strategy for packaging data, promoting efficient data movement and storage, and a dynamic on-/off-chip data storage management strategy, crucial for maintaining high throughput and low latency.”
From Model Quantization and Hardware Acceleration for Vision Transformers: A Comprehensive Survey (2024) · cites this paper as [22]
Huang et al. implement an integer-only quantization strategy for nonlinear operations to simplify computations, enhancing compatibility with edge devices.
“Huang et al. [22] implement an integer-only quantization strategy for nonlinear operations to simplify computations, enhancing compatibility with edge devices.”
From Model Quantization and Hardware Acceleration for Vision Transformers: A Comprehensive Survey (2024) · cites this paper as [22]
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References 29 · Cited by 77
- Authors
- Huang, M., Luo, J., Ding, C., Wei, Z., Huang, S., & Yu, H.
- Affiliations
- Chinese Academy of Sciences (CN)
- Southern University of Science and Technology (CN)
- Venue
- IEEE Transactions on Circuits and Systems I: Regular Papers
- Published
- 2023-12
- Volume
- 70
- Issue
- 12
- Pages
- 5289-5301
- ISSN
- 1549-8328 (ISSN-L)
- 1558-0806
- OpenAlex
- W4387789586
- Cited by
- 77
- References
- 29
- Citations by year
- 2026: 23 · 2025: 41 · 2024: 12 · 2023: 1
- FWCI
- 6.99
- Type
- journal article
- Language
- en
- Open access
- closed
- Licence
- Locations
- IEEE Transactions on Circuits and Systems I Regular Papers (publishedVersion)
- Funders
- STI 2030-Major Project (2022ZD0210600)
- National Natural Science Foundation of China (NSFC) through the Key Program (62034007)
- Shenzhen Science and Technology Program (KQTD20200820113051096, JCYJ20200109115210307)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Embedded Systems and FPGA Applications
- Keywords
- vision transformer, edge deployment, integer quantization, algorithm-hardware co-design, FPGA accelerator, multi-head self-attention, inference latency
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