Estimation of Upper Bound of Power Dissipation in QCA Circuits

Abstract

Quantum-dot cellular automata (QCA) is a field-coupled computing paradigm. States of a cell change due to mutual interactions of either electrostatic or magnetic fields. Due to their small sizes, power is an important design parameter. In this paper, we derive an upper bound for power loss that will occur with input change, even with the circuit staying at respective ground states before and after the change. This bound is computationally efficient to compute for large QCA circuits since it just requires the knowledge of the before and after ground states due to input change. We categorize power loss in clocked QCA circuits into two types that are commonly used in circuit theory: switching power and leakage power. Leakage power loss is independent of input states and occurs when the clock energy is raised or lowered to depolarize or polarize a cell. Switching power is dependent on input combinations and occurs at the instant when the cell actually changes state. Total power loss is controlled by changing the rate of change of transitions in the clocking function. Our model provides an estimate of power loss in a QCA circuit for clocks with sharp transitions, which result in nonadiabatic operations and gives us the upper bound of power expended. We derive expressions for upper bounds of switching and leakage power that are easy to compute. Upper bounds obviously are pessimistic estimates, but are necessary to design robust circuits, leaving room for operational manufacturing variability. Given that thermal issues are critical to QCA designs, we show how our model can be valuable for QCA design automation in multiple ways. It can be used to quickly locate potential thermal hot spots in a QCA circuit. The model can also be used to correlate power loss with different input vector switching; power loss is dependent on the input vector. We can study the tradeoff between switching and leakage power in QCA circuits. And, we can use the model to vet different designs of the same logic, which we demonstrate for the full adder.