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HIPAcc: A Domain-Specific Language and Compiler for Image Processing
Abstract
Domain-specific languages (DSLs) provide high-level and domain-specific abstractions that allow expressive and concise algorithm descriptions. Since the description in a DSL hides also the properties of the target hardware, DSLs are a promising path to target different parallel and heterogeneous hardware from the same algorithm description. In theory, the DSL description can capture all characteristics of the algorithm that are required to generate highly efficient parallel implementations. However, most frameworks do not make use of this knowledge and the performance cannot reach that of optimized library implementations. In this article, we present the HIPAccframework, a DSL and source-to-source compiler for image processing. We show that domain knowledge can be captured in the language and that this knowledge enables us to generate tailored implementations for a given target architecture. Back ends for CUDA, OpenCL, and Renderscript allow us to target discrete graphics processing units (GPUs) as well as mobile, embedded GPUs. Exploiting the captured domain knowledge, we can generate specialized algorithm variants that reach the maximal achievable performance due to the peak memory bandwidth. These implementations outperform state-of-the-art domain-specific languages and libraries significantly.
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A Combined Corner and Edge Detector
Harris, C., & Stephens, M. (1988) · Procedings of the Alvey Vision Conference 1988 · doi:10.5244/c.2.23 · Cited by 12,901
Bilateral Filtering for Gray and Color Images
Tomasi, C., & Manduchi, R. (2002) · Sixth International Conference on Computer Vision (IEEE Cat. No.98CH36271) · doi:10.1109/iccv.1998.710815 · Cited by 8,177 · cited 2×
“Consider the bilateral filter that combines a closeness component c and a similarity component s over a common sliding window [16].”
BackgroundMethodCompilers: Principles, Techniques, and Tools
Aho, A. V., Sethi, R., & Ullman, J. D. (1986) · Cited by 8,152
The Laplacian pyramid as a compact image code
Burt, P., & Adelson, E. (1983) · IEEE Transactions on Communications · doi:10.1109/tcom.1983.1095851 · Cited by 6,077
Williams, S., Waterman, A., & Patterson, D. A. (2009) · Communications of the ACM · doi:10.1145/1498765.1498785 · Cited by 2,798
Halstead, M. H. (1977) · CERN Document Server (European Organization for Nuclear Research) · Cited by 2,339
Russ, J. C. (2006) · CRC Press eBooks · doi:10.1201/9780203881095 · Cited by 2,202
High-Performance Compilers for Parallel Computing
Wolfe, M., Shanklin, C., & Ortega, L. (1995) · CERN Document Server (European Organization for Nuclear Research) · Cited by 1,288
Program development by stepwise refinement
Wirth, N. (1971) · Communications of the ACM · doi:10.1145/362575.362577 · Cited by 964
Intel threading building blocks : outfitting C++ for multi-core processor parallelism
Reinders, J. R. (2007) · Cited by 708
Research works printed but not linked: 2
- feautrier, 2011, Polyhedron model, Encyclopedia of Parallel Computing, 1581
- 2009, RapidMind Development Platform Documentation
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Metadata
- Authors
- Membarth, R., Reiche, O., Hannig, F., Teich, J., Korner, M., & Eckert, W.
- Affiliations
- German Research Centre for Artificial Intelligence (DE)
- Friedrich-Alexander-Universität Erlangen-Nürnberg (DE)
- Siemens (Germany) (DE)
- Venue
- IEEE Transactions on Parallel and Distributed Systems
- Published
- 2016-01-01
- Volume
- 27
- Issue
- 1
- Pages
- 210-224
- ISSN
- 1045-9219 (ISSN-L)
- OpenAlex
- W2075745057
- Semantic Scholar
- 57d70e927c9a1c2fc6c71f90336b071aa459eeb3
- Cited by
- 102
- References
- 41
- Citations by year
- 2026: 2 · 2025: 5 · 2024: 5 · 2023: 9 · 2022: 8 · 2021: 10 · 2020: 13 · 2019: 9 · 2018: 12 · 2017: 9 · 2016: 12
- FWCI
- 22.53
- Type
- journal article
- Language
- en
- Open access
- closed
- Locations
- IEEE Transactions on Parallel and Distributed Systems (publishedVersion)
- Funders
- German Research Foundation
- Research Training Group
- Topics
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Software › Model-Driven Software Engineering Techniques
- Keywords
- domain-specific languages, image processing, source-to-source compiler, GPU programming, CUDA, OpenCL, heterogeneous hardware, memory bandwidth optimization
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