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Safety analysis of timing properties in real-time systems

Jahanian, Farnam, Mok, Aloysius Ka-Lau·1986·IEEE Transactions on Software Engineering

Abstract

The authors formalize the safety analysis of timing properties in real-time systems. The analysis is based on a formal logic, RTL (real-time logic), which is especially suitable for reasoning about the timing behavior of systems. Given the formal specification of a system and a safety assertion to be analyzed, the goal is to relate the safety assertion to the systems specification. There are three distinct cases: (1) the safety assertion is a theorem derivable from the systems specification; (2) the safety assertion is unsatisfiable with respect to the systems specification; or (3) the negation of the safety assertion is satisfiable under certain conditions. A systematic method for performing safety analysis is presented.

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Metadata

Authors
Jahanian, F., & Mok, A. K.-L.
Venue
IEEE Transactions on Software Engineering
Published
1986-09
Volume
SE-12
Issue
9
Pages
890-904
ISSN
0098-5589 (ISSN-L)
OpenAlex
W2056359803
Cited by
628
References
0
FWCI
11.45
Type
journal article
Language
en
Open access
closed

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CoChat. (2026). Citation check: Safety analysis of timing properties in real-time systems. https://app.cochat.ai/papers/10.1109/tse.1986.6313045
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Jahanian, F., & Mok, A. K.-L. (1986). Safety analysis of timing properties in real-time systems. IEEE Transactions on Software Engineering. https://doi.org/10.1109/tse.1986.6313045

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