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VLSI cell placement techniques
Abstract
VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard cell and macro placement. Five major algorithms for placement are discussed: simulated annealing, force-directed placement, min-cut placement, placement by numerical optimization, and evolution-based placement. The first two classes of algorithms owe their origin to physical laws, the third and fourth are analytical techniques, and the fifth class of algorithms is derived from biological phenomena. In each category, the basic algorithm is explained with appropriate examples. Also discussed are the different implementations done by researchers.
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Cited by
Reconfigurable computing: a survey of systems and software
Compton, K., & Hauck, S. (2002) · ACM Computing Surveys · doi:10.1145/508352.508353 · Cited by 1,240
A graph placement methodology for fast chip design
Mirhoseini, A., Goldie, A., Yazgan, M., Jiang, J. W., Songhori, E., Wang, S., Lee, Y.-J., Johnson, E., Pathak, O., Nova, A., et al. (2021) · Nature · doi:10.1038/s41586-021-03544-w · Cited by 618
Metadata
- Authors
- Shahookar, K., & Mazumder, P.
- Venue
- ACM Computing Surveys
- Published
- 1991-06
- Volume
- 23
- Issue
- 2
- Pages
- 143-220
- ISSN
- 0360-0300 (ISSN-L)
- 1557-7341
- OpenAlex
- W2085374061
- Cited by
- 308
- References
- 0
- FWCI
- 12.45
- Type
- journal article
- Language
- en
- Open access
- closed
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- Shahookar, K., & Mazumder, P. (1991). VLSI cell placement techniques. ACM Computing Surveys. https://doi.org/10.1145/103724.103725
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