The DOI matches its Crossref record; 9 of the 9 references it cites were found in a registry or an index.
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
Abstract
Exploring architectures for large, modern FPGAs requires sophisticated software that can model and target hypothetical devices. Furthermore, research into new CAD algorithms often requires a complete and open source baseline CAD flow. This article describes recent advances in the open source Verilog-to-Routing (VTR) CAD flow that enable further research in these areas. VTR now supports designs with multiple clocks in both timing analysis and optimization. Hard adder/carry logic can be included in an architecture in various ways and significantly improves the performance of arithmetic circuits. The flow now models energy consumption, an increasingly important concern. The speed and quality of the packing algorithms have been significantly improved. VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. We also release new FPGA architecture files and models that are much closer to modern commercial architectures, enabling more realistic experiments. Finally, we show that while this version of VTR supports new and complex features, it has a 1.5× compile time speed-up for simple architectures and a 6× speed-up for complex architectures compared to the previous release, with no degradation to timing or wire-length quality.
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Citations
Cites
CMOS VLSI Design : A Circuits and Systems Perspective
Weste, N. H. E., & Harris, D. M. (2004) · Cited by 2,209
Architecture and CAD for Deep-Submicron FPGAS
Betz, V., Rose, J., & Marquardt, A. (1999) · Springer eBooks · doi:10.1007/978-1-4615-5145-4 · Cited by 1,352
Self-citationThe VTR project: architecture and CAD for FPGAs from verilog to routing
Rose, J., Luu, J., Yu, C. W., Densmore, O., Goeders, J., Somerville, A., Kent, K. B., Jamieson, P., & Anderson, J. (2012) · Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays · doi:10.1145/2145694.2145708 · Cited by 265
Self-citationA detailed power model for field-programmable gate arrays
Poon, K. K. W., Wilton, S. J. E., & Yan, A. (2005) · ACM Transactions on Design Automation of Electronic Systems · doi:10.1145/1059876.1059881 · Cited by 170
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
Jamieson, P., Kent, K. B., Gharibian, F., & Shannon, L. (2010) · 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines · doi:10.1109/fccm.2010.31 · Cited by 160
Self-citationPower modeling and characteristics of field programmable gate arrays
Li, F., Lin, Y., He, L., Chen, D., & Cong, J. (2005) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2005.852293 · Cited by 144
COFFE: Fully-automated transistor sizing for FPGAs
Chiasson, C., & Betz, V. (2013) · International Conference on Field-Programmable Technology (FPT) · doi:10.1109/fpt.2013.6718327 · Cited by 93
Self-citationSteiner, N., Wood, A., Shojaei, H., et al. (2011) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/1950413.1950425 · Cited by 92
Architecture-adaptive routability-driven placement for FPGAs
Sharma, A., Hauck, S., & Ebeling, C. (2005) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl.2005.1515759 · Cited by 39
Cited by
An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration
Li, Y., Li, X., Shen, H., Fan, J., Xu, Y., & Huang, K. (2024) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3640469 · Cited by 5
Metadata
- Authors
- Luu, J., Goeders, J., Wainberg, M., Somerville, A., Yu, T., Nasartschuk, K., Nasr, M., Wang, S., Liu, T., Ahmed, N., Kent, K. B., Anderson, J., Rose, J., & Betz, V.
- Venue
- ACM Transactions on Reconfigurable Technology and Systems
- Published
- 2014-06
- Volume
- 7
- Issue
- 2
- Pages
- 1-30
- ISSN
- 1936-7406 (ISSN-L)
- 1936-7414
- OpenAlex
- W2005602803
- Cited by
- 362
- References
- 9
- FWCI
- 23.35
- Type
- journal article
- Language
- en
- Open access
- closed
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- Luu, J., Goeders, J., Wainberg, M., Somerville, A., Yu, T., Nasartschuk, K., Nasr, M., Wang, S., Liu, T., Ahmed, N., Kent, K. B., Anderson, J., Rose, J., & Betz, V. (2014). VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Transactions on Reconfigurable Technology and Systems. https://doi.org/10.1145/2617593
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Contains information from the Semantic Scholar Academic Graph Datasets, made available under the ODC Attribution License (ODC-BY 1.0).
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