The DOI matches its Crossref record; 89 of the 89 references it cites were found in a registry or an index.
ISAAC: a convolutional neural network accelerator with in-situ analog arithmetic in crossbars
Abstract
A number of recent efforts have attempted to design accelerators for popular machine learning algorithms, such as those involving convolutional and deep neural networks (CNNs and DNNs). These algorithms typically involve a large number of multiply-accumulate (dot-product) operations. A recent project, DaDianNao, adopts a near data processing approach, where a specialized neural functional unit performs all the digital arithmetic operations and receives input weights from adjacent eDRAM banks. This work explores an in-situ processing approach, where memristor crossbar arrays not only store input weights, but are also used to perform dot-product operations in an analog manner. While the use of crossbar memory as an analog dot-product engine is well known, no prior work has designed or characterized a full-fledged accelerator based on crossbars. In particular, our work makes the following contributions: (i) We design a pipelined architecture, with some crossbars dedicated for each neural network layer, and eDRAM buffers that aggregate data between pipeline stages. (ii) We define new data encoding techniques that are amenable to analog computations and that can reduce the high overheads of analog-to-digital conversion (ADC). (iii) We define the many supporting digital components required in an analog CNN accelerator and carry out a design space exploration to identify the best balance of memristor storage/compute, ADCs, and eDRAM storage on a chip. On a suite of CNN and DNN workloads, the proposed ISAAC architecture yields improvements of 14.8×, 5.5×, and 7.5× in throughput, energy, and computational density (respectively), relative to the state-of-the-art DaDianNao architecture.
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Cites
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Research works printed but not linked: 1
- B. Murmann "ADC Performance Survey 1997-2015 (ISSCC & VLSI Symposium) " 2015 http://web.stanford.edu/~murmann/adcsurvey.html. B. Murmann "ADC Performance Survey 1997-2015 (ISSCC & VLSI Symposium) " 2015 http://web.stanford.edu/~murmann/adcsurvey.html.
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In-Datacenter Performance Analysis of a Tensor Processing Unit
Jouppi, N. P., Young, C., Patil, N., Patterson, D., Agrawal, G., Bajwa, R., Bates, S., Bhatia, S., Boden, N., Borchers, A., et al. (2017) · Proceedings of the 44th Annual International Symposium on Computer Architecture · doi:10.1145/3079856.3080246 · Cited by 4,537
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
Sze, V., Chen, Y.-H., Yang, T.-J., & Emer, J. S. (2017) · Proceedings of the IEEE · doi:10.1109/jproc.2017.2761740 · Cited by 4,215
“(b) Gi is conductance of resistive memory (Figure from [106]).”
BackgroundMethodDeep learning with coherent nanophotonic circuits
Shen, Y., Harris, N. C., Skirlo, S., Prabhu, M., Baehr-Jones, T., Hochberg, M., Sun, X., Zhao, S., Larochelle, H., Englund, D., et al. (2017) · Nature Photonics · doi:10.1038/nphoton.2017.93 · Cited by 3,340
Memory devices and applications for in-memory computing
Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R., & Eleftheriou, E. (2020) · Nature Nanotechnology · doi:10.1038/s41565-020-0655-z · Cited by 2,289
The future of electronics based on memristive systems
Zidan, M. A., Strachan, J. P., & Lu, W. D. (2018) · Nature Electronics · doi:10.1038/s41928-017-0006-8 · Cited by 2,138
Self-citation
Metadata
- Authors
- Shafiee, A., Nag, A., Muralimanohar, N., Balasubramonian, R., Strachan, J. P., Hu, M., Williams, R. S., & Srikumar, V.
- Venue
- ACM SIGARCH Computer Architecture News
- Published
- 2016-06-18
- Volume
- 44
- Issue
- 3
- Pages
- 14-26
- ISSN
- 0163-5964 (ISSN-L)
- OpenAlex
- W2518281301
- Cited by
- 1,536
- References
- 89
- FWCI
- 63.88
- Type
- journal article
- Language
- en
- Open access
- closed
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