The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.
An OpenCL™ Deep Learning Accelerator on Arria 10
Abstract
Convolutional neural nets (CNNs) have become a practical means to perform vision tasks, particularly in the area of image classification. FPGAs are well known to be able to perform convolutions efficiently, however, most recent efforts to run CNNs on FPGAs have shown limited advantages over other devices such as GPUs. Previous approaches on FPGAs have often been memory bound due to the limited external memory bandwidth on the FPGA device. We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth. Furthermore, we show how we can use the Winograd transform to significantly boost the performance of the FPGA. As a result, when running our DLA on Intel's Arria 10 device we can achieve a performance of 1020 img/s, or 23 img/s/W when running the AlexNet CNN benchmark. This comes to 1382 GFLOPs and is 10x faster with 8.4x more GFLOPS and 5.8x better efficiency than the state-of-the-art on FPGAs. Additionally, 23 img/s/W is competitive against the best publicly known implementation of AlexNet on nVidia's TitanX GPU.
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Cites
ImageNet classification with deep convolutional neural networks
Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155
Going Deeper with Convolutions
Szegedy, C., Liu, W., Jia, Y., Sermanet, P., Reed, S., Anguelov, D., Erhan, D., Vanhoucke, V., & Rabinovich, A. (2014) · arXiv · doi:10.48550/arxiv.1409.4842 · Cited by 1,461
Deep Learning with Limited Numerical Precision
Gupta, S., Agrawal, A., Gopalakrishnan, K., & Narayanan, P. (2015) · arXiv · doi:10.48550/arxiv.1502.02551 · Cited by 1,364
Cited by
A High-Throughput and Power-Efficient FPGA Implementation of YOLO CNN for Object Detection
Nguyen, D. T., Nguyen, T. N., Kim, H., & Lee, H.-J. (2019) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2019.2905242 · Cited by 435
A survey of FPGA-based accelerators for convolutional neural networks
Mittal, S. (2020) · Neural Computing and Applications · doi:10.1007/s00521-018-3761-1 · Cited by 429
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs
Wei, X., Yu, C. H., Zhang, P., Chen, Y., Wang, Y., Hu, H., Liang, Y., & Cong, J. (2017) · Proceedings of the 54th Annual Design Automation Conference 2017 · doi:10.1145/3061639.3062207 · Cited by 426
[DL] A Survey of FPGA-based Neural Network Inference Accelerators
Guo, K., Zeng, S., Yu, J., Wang, Y., & Yang, H. (2019) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3289185 · Cited by 292
Li, S., Luo, Y., Sun, K., Yadav, N., & Choi, K. K. (2020) · IEEE Access · doi:10.1109/access.2020.3000009 · Cited by 75
Metadata
- Authors
- Aydonat, U., O'Connell, S., Capalija, D., Ling, A. C., & Chiu, G. R.
- Venue
- Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
- Publisher
- ACM
- Published
- 2017-02-22
- Pages
- 55-64
- OpenAlex
- W2574797063
- Cited by
- 229
- References
- 3
- FWCI
- 12.22
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Aydonat, U., O'Connell, S., Capalija, D., Ling, A. C., & Chiu, G. R. (2017). An OpenCL™ Deep Learning Accelerator on Arria 10. Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. https://doi.org/10.1145/3020078.3021738
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