The DOI matches its Crossref record.
A 0.57-GOPS/DSP Object Detection PIM Accelerator on FPGA
Abstract
The paper presents an object detection accelerator featuring a processing-in-memory (PIM) architecture on FPGAs. PIM architectures are well known for their energy efficiency and avoidance of the memory wall. In the accelerator, a PIM unit is developed using BRAM and LUT based counters, which also helps to improve the DSP performance density. The overall architecture consists of 64 PIM units and three memory buffers to store inter-layer results. A shrunk and quantized Tiny-YOLO network is mapped to the PIM accelerator, where DRAM access is fully eliminated during inference. The design achieves a throughput of 201.6 GOPs at 100MHz clock rate and correspondingly, a performance density of 0.57 GOPS/DSP.
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The setup in Jiao et al. (2021) leverages a high throughput of 201.6 GOPs at 100 MHz processor frequency.
“It is shown that the setup can leverage a high throughput of 201.6GOPs at 100 MHz processor frequency.”
From A review on TinyML: State-of-the-art and prospects (2022) · cites this paper as Jiao et al., 2021
The design in Jiao et al. (2021) eliminates the need for off-chip memory access, improving processing time with low-bit-width quantization.
“The design eliminates the need of off-chip memory access thus improving processing time with a low-bit-width quantization facility.”
From A review on TinyML: State-of-the-art and prospects (2022) · cites this paper as Jiao et al., 2021
Citations
Cites
No references could be resolved yet.
Research works printed but not linked: 5
- Cai Y., 2018, Training low bitwidth convolutional neural network on RRAM, Asia and South Pacific Design Automation Conference (ASP-DAC), 117
- Wang D., 2019, ABM-SpConv: A Novel Approach to FPGA-Based Acceleration of Convolutional Neural Network Inference," in 2019 56th ACM/IEEE Design Automation Conference (DAC), 1
- 10.1109/MDAT.2019.2952329 · DOI
- Esser S.K., 2020, International Conference on Learning Representations 2020 (ICLR)
- Redmon J., 2018, An Incremental Improvement," [On-line]Available: https://arxiv.org/abs/1804.02767 · arXiv
Cited by
Sorted by citations
A review on TinyML: State-of-the-art and prospects
Ray, P. P. (2022) · Journal of King Saud University - Computer and Information Sciences · doi:10.1016/j.jksuci.2021.11.019 · Cited by 460
“Similar type of PIM is presented in (Jiao et al., 2021) where a shrunk network is deployed along with a Tiny-YOLO network.”
Metadata
- Authors
- Jiao, B., Zhang, J., Xie, Y., Wang, S., Zhu, H., Kang, X., Dong, Z., Zhang, L., & Chen, C.
- Affiliations
- Fudan University (CN)
- ORCID
- Venue
- Proceedings of the 26th Asia and South Pacific Design Automation Conference
- Publisher
- ACM
- Published
- 2021-01-18
- Pages
- 13-14
- OpenAlex
- W3128155691
- Cited by
- 8
- References
- 0
- Citations by year
- 2026: 1 · 2023: 1 · 2022: 5 · 2021: 1
- FWCI
- 0.57
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Asia and South Pacific Design Automation Conference (ASP-DAC) (publishedVersion)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
- Physical Sciences › Computer Science › Hardware and Architecture › Network Packet Processing and Optimization
- Keywords
- in-memory computing, FPGA, Tiny-YOLO, memory wall, energy efficiency, inference acceleration
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