CoChat
Sign Up
Cited by 52VLSI and FPGA Design TechniquesLow-power high-performance VLSI designEmbedded Systems Design Techniques

AutoDMP: Automated DREAMPlace-based Macro Placement

Open access
Agnesina, Anthony, Rajvanshi, Puranjay, Yang, Tian, Pradipta, Geraldo, Jiao, Austin, Keller, Ben, Khailany, Brucek, Ren, Haoxing·2023·Proceedings of the 2023 International Symposium on Physical Design
DOI 10.1145/3569052.3578923
Open this paper in CoChat — free accountOpen PDF

Abstract

Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated placer, to place macros and standard cells concurrently in conjunction with automated parameter tuning using a multi-objective hyperparameter optimization technique. As a result, we can generate high-quality predictable solutions, improving the macro placement quality of academic benchmarks compared to baseline results generated from academic and commercial tools. AutoDMP is also computationally efficient, optimizing a design with 2.7 million cells and 320 macros in 3 hours on a single NVIDIA DGX Station A100. This work demonstrates the promise and potential of combining GPU-accelerated algorithms and ML techniques for VLSI design automation.

The claims and statistics of this paper haven’t been checked yet.

Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.

A few free checks a day · papers already verified open instantly · results are public

Integrity signals

Registry

Crossref · 10.1145/3569052.3578923

Cites

Statistics

Claims the paper makes

The claims and statistics of this paper haven’t been checked yet.

Run the check — free, no account needed. It reads the open-access text and checks the sources it cites.

A few free checks a day · papers already verified open instantly · results are public

Claims other papers make about this one

Each is checked against this paper’s own text: does it say what the citing paper says it does?

  • The combination of advanced AI agents could eventually lead to recursive self-improvement at the collective level.

    “More speculatively, the combination of advanced AI agents could eventually lead to recursive self-improvement at the collective level, as AI research itself becomes increasingly automated (Agnesina et al., 2023; Hutter et al., 2019; Lu et al., 2024a; Mankowitz et al., 2023), even though no individual system possesses this capability.”

    From Multi-Agent Risks from Advanced AI (2025) · cites this paper as Agnesina et al., 2023

    The AutoDMP Framework (§4) and Conclusion (§6; page numbers unavailable) describe automated VLSI macro placement, not AI agents improving AI research. Searches for recursive self-improvement, collective AI agents, and automation of AI research found no passage addressing the attributed claim. (LLM, conf=0.76)

    Experimental — accuracy not yet measured

Self-check

Percentages, sums and reported differences re-computed from the paper’s own numbers.

The self-check needs the paper’s full text.

Cites

No references could be resolved yet.

Research works printed but not linked: 49

  1. S. N. Adya and I. L. Markov. Combinatorial techniques for mixed-size placement. ACM Transactions on Design Automation of Electronic Systems (TODAES), 10(1):58- 90, 2005.
  2. C. Alpert, Z. Li, G.-J. Nam, C. N. Sze, N. Viswanathan, and S. I. Ward. Placement: Hot or not? In Proceedings of the International Conference on Computer-Aided Design, pages 283-290, 2012.
  3. L. Armijo. Minimization of functions having Lipschitz continuous first partial derivatives. Pacific Journal of mathematics, 16(1):1-3, 1966.
  4. J. Bergstra, R. Bardenet, Y. Bengio, and B. Kégl. Algorithms for hyper-parameter optimization. Advances in neural information processing systems, 24, 2011.
  5. U. Brenner, M. Struzyna, and J. Vygen. BonnPlace: Placement of leading-edge chips by advanced combinatorial algorithms. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 27(9):1607-1620, 2008.
  6. T. F. Chan, K. Sze, J. R. Shinnerl, and M. Xie. mPL6: Enhanced multilevel mixed- size placement with congestion control. Modern Circuit Placement: Best Practices and Results, pages 247-288, 2007.
  7. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu. B*-Trees: A New Represen- tation for Non-Slicing Floorplans. In ACM/IEEE Design Automation Conference (DAC), pages 458-463, 2000.
  8. H.-C. Chen, Y.-L. Chuang, Y.-W. Chang, and Y.-C. Chang. Constraint graph-based macro placement for modern mixed-size circuit designs. In 2008 IEEE/ACM International Conference on Computer-Aided Design, pages 218-223. IEEE, 2008.
  9. T.-C. Chen and Y.-W. Chang. Modern floorplanning based on fast simulated annealing. In Proceedings of the 2005 international symposium on Physical design, pages 104-112, 2005.
  10. T.-C. Chen, Y.-W. Chang, and S.-C. Lin. IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs. In ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005., pages 159-164. IEEE, 2005.
  11. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang. NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 27(7):1228-1240, 2008.
  12. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu. MP-trees: A packing- based macro placement algorithm for mixed-size designs. In Proceedings of the 44th annual Design Automation Conference, pages 447-452, 2007.
  13. C. Cheng, A. B. Kahng, I. Kang, and L. Wang. RePlAce: Advancing Solution Quality and Routability Validation in Global Placement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 38(9):1717- 1730, 2019.
  14. C.-K. Cheng, A. B. Kahng, S. Kundu, Y. Wang, and Z. Wang. Assessment of Reinforcement Learning for Macro Placement. In ACM International Symposium on Physical Design (ISPD), 2023.
  15. C.-L. E. Cheng. RISA: Accurate and efficient placement routability modeling. In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 690-695, 1994.
  16. C. Chu and Y.-C. Wong. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 27(1):70-83, 2008.
  17. L. T. Clark, V. Vashishtha, L. Shifren, A. Gujja, S. Sinha, B. Cline, C. Ramamurthy, and G. Yeric. ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal, 53:105-115, 2016.
  18. J. Cong, M. Romesis, and J. R. Shinnerl. Fast floorplanning by look-ahead enabled recursive bipartitioning. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, pages 1119-1122, 2005.
  19. P.-N. Guo, C.-K. Cheng, and T. Yoshimura. An O-tree representation of non- slicing floorplan and its applications. In Proceedings 1999 design automation conference, pages 268-273. IEEE, 1999.
  20. X. Hong and S. Dong. Non-slicing floorplan and placement using corner block list topological representation. IEEE Transactions on Circuits and Systems II: Express Briefs, 51, 2004.
  21. M.-K. Hsu, V. Balabanov, and Y.-W. Chang. TSV-aware analytical placement for 3-D IC designs based on a novel weighted-average wirelength model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2013.
  22. M.-K. Hsu and Y.-W. Chang. Unified analytical global placement for large- scale mixed-size circuit designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(9):1366-1378, 2012.
  23. F. Hutter, H. H. Hoos, and K. Leyton-Brown. Sequential Model-Based Optimiza- tion for General Algorithm Configuration. In Proceedings of the 5th International Conference on Learning and Intelligent Optimization, LION'05, page 507-523, Berlin, Heidelberg, 2011. Springer-Verlag.
  24. S. Izquierdo, J. Guerrero-Viu, S. Hauns, G. Miotto, S. Schrodi, A. Biedenkapp, T. Elsken, D. Deng, M. Lindauer, and F. Hutter. Bag of baselines for multi-objective joint neural architecture search and hyperparameter optimization. In 8th ICML Workshop on Automated Machine Learning (AutoML), 2021.
  25. A. B. Kahng. Advancing placement. In ACM International Symposium on Physical Design (ISPD), pages 15-22, 2021.
  26. A. B. Kahng, S. Reda, and Q. Wang. Architecture and details of a high quality, large-scale analytical placer. In IEEE/ACM International Conference on Computer- Aided Design (ICCAD), pages 891-898, 2005.
  27. A. B. Kahng, R. Varadarajan, and Z. Wang. RTL-MP: Toward Practical, Human- Quality Chip Planning and Macro Placement. In ACM International Symposium on Physical Design (ISPD), pages 3-11, 2022.
  28. D. P. Kingma and J. Ba. Adam: A method for stochastic optimization. arXiv preprint arXiv:1412.6980, 2014. · arXiv
  29. P. Liao, S. Liu, Z. Chen, W. Lv, Y. Lin, and B. Yu. DREAMPlace 4.0: Timing- driven global placement with momentum-based net weighting. In 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022.
  30. Y. Lin, S. Dhar, W. Li, H. Ren, B. Khailany, and D. Z. Pan. DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement. In ACM/IEEE Design Automation Conference (DAC), 2019.
  31. Y. Lin, W. Li, J. Gu, H. Ren, B. Khailany, and D. Z. Pan. ABCDPlace: Accelerated Batch-based Concurrent Detailed Placement on Multi-threaded CPUs and GPUs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pages 1-1, 2020.
  32. Y. Lin, D. Z. Pan, H. Ren, and B. Khailany. DREAMPlace 2.0: Open-Source GPU- Accelerated Global and Detailed Placement for Large-Scale VLSI Designs. In 2020 China Semiconductor Technology International Conference (CSTIC), pages 1-4. IEEE, 2020.
  33. H.-Y. Liu and L. P. Carloni. On learning-based methods for design-space explo- ration with High-Level Synthesis. In 2013 50th ACM/EDAC/IEEE Design Automa- tion Conference (DAC), pages 1-7, 2013.
  34. Y.-C. Liu, T.-C. Chen, Y.-W. Chang, and S.-Y. Kuo. MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. In Proceedings of the 24th Asia and South Pacific Design Automation Conference, pages 557-562, 2019.
  35. S. Lloyd. Least squares quantization in PCM. IEEE transactions on information theory, 28(2):129-137, 1982.
  36. J. Lu, H. Zhuang, P. Chen, H. Chang, C.-C. Chang, Y.-C. Wong, L. Sha, D. Huang, Y. Luo, C.-C. Teng, et al. ePlace-MS: Electrostatics-Based Placement for Mixed- Size Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 34(5):685-698, 2015.
  37. I. L. Markov, J. Hu, and M.-C. Kim. Progress and challenges in VLSI placement research. Proceedings of the IEEE, 103(11):1985-2003, 2015.
  38. A. Mirhoseini, A. Goldie, M. Yazgan, J. W. Jiang, E. Songhori, S. Wang, Y.-J. Lee, E. Johnson, O. Pathak, A. Nazi, et al. A graph placement methodology for fast chip design. Nature, 594(7862):207-212, 2021.
  39. H. Murata, K. Fujiyoshi, S. Nakatake, and Y. Kajitani. VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems (TCAD), 12:1518-1524, 1996.
  40. Y. Nesterov. Introductory lectures on convex optimization: A basic course, volume 87. Springer Science & Business Media, 2003.
  41. Y. Ozaki, Y. Tanigaki, S. Watanabe, and M. Onishi. Multiobjective Tree-Structured Parzen Estimator for Computationally Expensive Optimization Problems. In Pro- ceedings of the 2020 Genetic and Evolutionary Computation Conference, GECCO '20, page 533-541, New York, NY, USA, 2020. Association for Computing Machinery.
  42. E. Parzen. On estimation of a probability density function and mode. The annals of mathematical statistics, 33(3):1065-1076, 1962.
  43. A. Ranjan, K. Bazargan, S. Ogrenci, and M. Sarrafzadeh. Fast floorplanning for effective prediction and construction. IEEE transactions on very large scale integration (VLSI) systems, 9(2):341-351, 2001.
  44. P. G. Sassone and S. K. Lim. A novel geometric algorithm for fast wire-optimized floorplanning. In ICCAD-2003. International Conference on Computer Aided Design, pages 74-80. IEEE, 2003.
  45. C.-W. Sham, F. Y. Young, and C. Chu. Optimal cell flipping in placement and floorplanning. In ACM/IEEE Design Automation Conference (DAC), pages 1109- 1114, 2006.
  46. P. Spindler and F. M. Johannes. Fast and accurate routing demand estimation for efficient routability-driven placement. In IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), pages 1-6. IEEE, 2007.
  47. Z. Xie, G.-Q. Fang, Y.-H. Huang, H. Ren, Y. Zhang, B. Khailany, S.-Y. Fang, J. Hu, Y. Chen, and E. C. Barboza. FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. In 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), pages 19-25, 2020.
  48. J. Z. Yan and C. Chu. DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanner. In ACM/IEEE Design Automation Conference (DAC), pages 161-166, 2008.
  49. J. Z. Yan, N. Viswanathan, and C. Chu. Handling complexities in modern large- scale mixed-size placement. In Proceedings of the 46th Annual Design Automation Conference, pages 436-441, 2009.

Cited by

Sorted by citations

Authors
Agnesina, A., Rajvanshi, P., Yang, T., Pradipta, G., Jiao, A., Keller, B., Khailany, B., & Ren, H.
Affiliations
Nvidia (United States) (US)
ORCID
Venue
Proceedings of the 2023 International Symposium on Physical Design
Publisher
ACM
Published
2023-03-26
Pages
149-157
DOI
10.1145/3569052.3578923
OpenAlex
W4353031976
Cited by
52
References
0
Citations by year
2026: 11 · 2025: 22 · 2024: 13 · 2023: 6
FWCI
25.50
Type
conference paper
Language
en
Open access
Licence
Locations
International Symposium on Physical Design (publishedVersion, cc-by)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
  • Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
Keywords
macro placement, VLSI physical design, auto-tuning, VLSI design automation

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review