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The architecture of the DIVA processing-in-memory chip
Abstract
The DIVA (Data IntensiVe Architecture) system incorporates a collection of Processing-In-Memory (PIM) chips as smart-memory co-processors to a conventional microprocessor. We have recently fabricated prototype DIVA PIMs. These chips represent the first smart-memory devices designed to support virtual addressing and capable of executing multiple threads of control. In this paper, we describe the prototype PIM architecture. We emphasize three unique features of DIVA PIMs, namely, the memory interface to the host processor, the 256-bit wide datapaths for exploiting on-chip bandwidth, and the address translation unit. We present detailed simulation results on eight benchmark applications. When just a single PIM chip is used, we achieve an average speedup of 3.3X over host-only execution, due to lower memory stall times and increased fine-grain parallelism. These 1-PIM results suggest that a PIM-based architecture with many such chips yields significantly higher performance than a multiprocessor of a similar scale and at a much reduced hardware cost.
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Improving the ratio of memory operations to floating-point operations in loops
Carr, S., & Kennedy, K. (1994) · ACM Transactions on Programming Languages and Systems · doi:10.1145/197320.197366 · Cited by 155
Cited by
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Song, L., Qian, X., Li, H., & Chen, Y. (2017) · 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) · doi:10.1109/hpca.2017.55 · Cited by 833
Computing in Memory With Spin-Transfer Torque Magnetic RAM
Jain, S., Ranjan, A., Roy, K., & Raghunathan, A. (2018) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2017.2776954 · Cited by 355
Metadata
- Authors
- Draper, J., Chame, J., Hall, M., Steele, C., Barrett, T., LaCoss, J., Granacki, J., Shin, J., Chen, C., Kang, C. W., Kim, I., & Daglikoca, G.
- Venue
- Proceedings of the 16th international conference on Supercomputing
- Publisher
- ACM
- Published
- 2002-06-22
- Pages
- 14-25
- OpenAlex
- W2094332102
- Cited by
- 204
- References
- 1
- FWCI
- 5.19
- Type
- conference paper
- Language
- en
- Open access
- closed
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- Draper, J., Chame, J., Hall, M., Steele, C., Barrett, T., LaCoss, J., Granacki, J., Shin, J., Chen, C., Kang, C. W., Kim, I., & Daglikoca, G. (2002). The architecture of the DIVA processing-in-memory chip. Proceedings of the 16th international conference on Supercomputing. https://doi.org/10.1145/514191.514197
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