Si, Xin

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors

Khwa, W.-S., Chen, J.-J., Li, J.-F., Si, X., Yang, E.-Y., Sun, X., Liu, R., Chen, P.-Y., Li, Q., Yu, S., et al. (2018) · 2018 IEEE International Solid - State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 260

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

Su, J.-W., Chou, Y.-C., Liu, R., Liu, T.-W., Lu, P.-J., Wu, P.-C., Chung, Y.-L., Hung, L.-Y., Ren, J.-S., Pan, T., et al. (2021) · 2021 IEEE International Solid-State Circuits Conference (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 207

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips

Su, J.-W., Si, X., Chou, Y.-C., Chang, T.-W., Huang, W.-H., Tu, Y.-N., Liu, R., Lu, P.-J., Liu, T.-W., Wang, J.-H., et al. (2020) · 2020 IEEE International Solid- State Circuits Conference - (ISSCC)

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 189

A computing-in-memory macro based on three-dimensional resistive random-access memory

Huo, Q., Yang, Y., Wang, Y., Lei, D., Fu, X., Ren, Q., Xu, X., Luo, Q., Xing, G., Chen, C., et al. (2022) · Nature Electronics

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 159