Dally, William J.

SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <0.5MB model size

Iandola, F. N., Han, S., Moskewicz, M. W., Ashraf, K., Dally, W. J., & Keutzer, K. (2016) · arXiv

Advanced Neural Network ApplicationsDomain Adaptation and Few-Shot Learning

Cited by 6,201

Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding

Han, S., Mao, H., & Dally, W. J. (2015) · arXiv

Advanced Neural Network ApplicationsAdvanced Data Compression Techniques

Cited by 4,662

EIE: efficient inference engine on compressed deep neural network

Han, S., Liu, X., Mao, H., Pu, J., Pedram, A., Horowitz, M. A., & Dally, W. J. (2016) · ACM SIGARCH Computer Architecture News

Advanced Neural Network ApplicationsParallel Computing and Optimization Techniques

Cited by 1,937

Learning both Weights and Connections for Efficient Neural Networks

Han, S., Pool, J., Tran, J., & Dally, W. J. (2015) · arXiv

Advanced Neural Network ApplicationsMachine Learning and Data Classification

Cited by 1,481

Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training

Lin, Y., Han, S., Mao, H., Wang, Y., & Dally, W. J. (2017) · arXiv

Stochastic Gradient Optimization TechniquesMachine Learning and Data Classification

Cited by 1,134

EIE: Efficient Inference Engine on Compressed Deep Neural Network

Han, S., Liu, X., Mao, H., Pu, J., Pedram, A., Horowitz, M. A., & Dally, W. J. (2016) · 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)

Advanced Neural Network ApplicationsParallel Computing and Optimization Techniques

Cited by 1,077

Trained Ternary Quantization

Zhu, C., Han, S., Mao, H., & Dally, W. J. (2016) · arXiv

Advanced Neural Network ApplicationsDomain Adaptation and Few-Shot Learning

Cited by 865

Exploring the Regularity of Sparse Structure in Convolutional Neural Networks

Mao, H., Han, S., Pool, J., Li, W., Liu, X., Wang, Y., & Dally, W. J. (2017) · arXiv

Advanced Neural Network ApplicationsParallel Computing and Optimization Techniques

Cited by 219

A 0.32–128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm

Zimmer, B., Venkatesan, R., Shao, Y. S., Clemons, J., Fojtik, M., Jiang, N., Keller, B., Klinefelter, A., Pinckney, N., Raina, P., et al. (2020) · IEEE Journal of Solid-State Circuits

Advanced Neural Network ApplicationsInterconnection Networks and Systems

Cited by 122

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference

Rekhi, A. S., Zimmer, B., Nedovic, N., Liu, N., Venkatesan, R., Wang, M., Khailany, B., Dally, W. J., & Gray, C. T. (2019) · Proceedings of the 56th Annual Design Automation Conference 2019

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 67