EIE: Efficient Inference Engine on Compressed Deep Neural Network
Open accessAbstract
State-of-the-art deep neural networks (DNNs) have hundreds of millions of connections and are both computationally and memory intensive, making them difficult to deploy on embedded systems with limited hardware resources and power budgets. While custom hardware helps the computation, fetching weights from DRAM is two orders of magnitude more expensive than ALU operations, and dominates the required power. Previously proposed 'Deep Compression' makes it possible to fit large DNNs (AlexNet and VGGNet) fully in on-chip SRAM. This compression is achieved by pruning the redundant connections and having multiple connections share the same weight. We propose an energy efficient inference engine (EIE) that performs inference on this compressed network model and accelerates the resulting sparse matrix-vector multiplication with weight sharing. Going from DRAM to SRAM gives EIE 120x energy saving, Exploiting sparsity saves 10x, Weight sharing gives 8x, Skipping zero activations from ReLU saves another 3x. Evaluated on nine DNN benchmarks, EIE is 189x and 13x faster when compared to CPU and GPU implementations of the same DNN without compression. EIE has a processing power of 102 GOPS working directly on a compressed network, corresponding to 3 TOPS on an uncompressed network, and processes FC layers of AlexNet at 1.88x104 frames/sec with a power dissipation of only 600mW. It is 24,000x and 3,400x more energy efficient than a CPU and GPU respectively. Compared with DaDianNao, EIE has 2.9x, 19x and 3x better throughput, energy efficiency and area efficiency.
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The DSCC can save a lot of energy when implementing VMM operations between sparse matrices or when the readout current of RRAM is small.
“which elucidates that it can save a lot of energy when implementing the VMM operations between sparse matrices (such as sparse weights) 34 or the readout current of RRAM is small.”
From A computing-in-memory macro based on three-dimensional resistive random-access memory (2022) · cites this paper as [34]
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- Authors
- Han, S., Liu, X., Mao, H., Pu, J., Pedram, A., Horowitz, M. A., & Dally, W. J.
- Affiliations
- Stanford University (US)
- Nvidia (United Kingdom) (GB)
- Venue
- 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)
- Publisher
- IEEE
- Published
- 2016-06
- Pages
- 243-254
- ISSN
- 1063-6897 (ISSN-L)
- OpenAlex
- W2950656546
- Cited by
- 1,077
- References
- 5
- Citations by year
- 2026: 37 · 2025: 70 · 2024: 71 · 2023: 119 · 2022: 120 · 2021: 95 · 2020: 129 · 2019: 163 · 2018: 149 · 2017: 94 · 2016: 29 · 2015: 1
- FWCI
- 50.29
- Type
- conference paper
- Language
- en
- Update notices
- new_edition (2016-06-18)
- Open access
- green
- arxiv.org
- Locations
- Proceedings - International Symposium on Computer Architecture/Proceedings (publishedVersion)
- arXiv (Cornell University) (submittedVersion)
- arXiv (Cornell University)
- Topics
- Physical Sciences › Computer Science › Computer Vision and Pattern Recognition › Advanced Neural Network Applications
- Physical Sciences › Computer Science › Hardware and Architecture › Parallel Computing and Optimization Techniques
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
- Keywords
- deep neural network compression, inference engine, energy efficiency, sparse matrix-vector multiplication, parameter sharing, connection pruning, embedded systems, AlexNet, VGG, hardware acceleration
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