Francese, Pier Andrea

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

Kull, L., Toifl, T., Schmatz, M., Francese, P. A., Menolfi, C., Brandli, M., Kossel, M., Morf, T., Andersen, T. M., & Leblebici, Y. (2013) · IEEE Journal of Solid-State Circuits

Analog and Mixed-Signal Circuit DesignRadio Frequency Integrated Circuit Design

Cited by 347

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., et al. (2023) · Nature Electronics

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 310

HERMES-Core—A 1.59-TOPS/mm 2 PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Brändli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2022) · IEEE Journal of Solid-State Circuits

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 144

HERMES Core – A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing

Khaddam-Aljameh, R., Stanisavljevic, M., Fornt Mas, J., Karunaratne, G., Braendli, M., Liu, F., Singh, A., Müller, S. M., Egger, U., Petropoulos, A., et al. (2021) · 2021 Symposium on VLSI Circuits

Advanced Memory and Neural ComputingLow-power high-performance VLSI design

Cited by 124

5 Parallel Prism: A topology for pipelined implementations of convolutional neural networks using computational memory

Dazzi, M., Sebastian, A., Francese, P. A., Parnell, T., Benini, L., & Eleftheriou, E. (2019) · arXiv

Advanced Memory and Neural ComputingParallel Computing and Optimization Techniques

Cited by 10