CoChat
Sign Up
Cited by 310Advanced Memory and Neural ComputingLow-power high-performance VLSI designAnalog and Mixed-Signal Circuit Design

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

Open access
Le Gallo, Manuel, Khaddam-Aljameh, Riduan, Stanisavljevic, Milos, Vasilopoulos, Athanasios, Kersting, Benedikt, Dazzi, Martino, Karunaratne, Geethan, Brändli, Matthias +22 more·2023·Nature Electronics
DOI 10.1038/s41928-023-01010-1
Open this paper in CoChat — free accountOpen PDF

Abstract

A multicore analogue in-memory computing chip that is designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory can be used for deep neural network inference. Analogue in-memory computing (AIMC) with resistive memory devices could reduce the latency and energy consumption of deep neural network inference tasks by directly performing computations within memory. However, to achieve end-to-end improvements in latency and energy consumption, AIMC must be combined with on-chip digital operations and on-chip communication. Here we report a multicore AIMC chip designed and fabricated in 14 nm complementary metal–oxide–semiconductor technology with backend-integrated phase-change memory. The fully integrated chip features 64 AIMC cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units. With this approach, we demonstrate near-software-equivalent inference accuracy with ResNet and long short-term memory networks, while implementing all the computations associated with the weight layers and the activation functions on the chip. For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.

AI snapshot

Written from a shortened version of the paper’s full text (it is longer than we read).

TL;DR

Hermes is a 64-core analog in-memory compute chip in 14-nm CMOS with backend-integrated phase-change memory, designed to run deep neural network inference with on-chip digital operations and communication. It demonstrates near software-equivalent accuracy on ResNet and LSTM tasks while achieving 63.1 TOPS and 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.

Key findings

  • The chip contains 64 cores, each with a 256×256 PCM crossbar, enabling up to 4,194,304 weights on-chip; it is fabricated in 14-nm CMOS, measures 12 mm × 12 mm, and uses 418 communication links implementing a 5 Parallel Prism topology.
  • On 63 of 64 cores, more than 99% of unit cells can be programmed to |G_RESET| smaller than 5 ADC counts and G_SET larger than 50 ADC counts; the outlier core has 98.4% yield. One-device-per-weight (ODP) programming achieves precision close to 3-bit weights, while two-device-per-weight (TDP) achieves between 3-bit and 4-bit weights.
  • For ResNet-9 on CIFAR-10, Hermes achieves 92.81% accuracy with TDP and 92.23% with ODP, versus a software baseline of 93.67%; digital quantization adds another 0.2–0.3% drop. The chip reaches a maximal throughput of 63.1 TOPS at 9.76 TOPS W−1 for 8-bit input/output MVMs, with MVM throughput per area >15× higher than comparable multi-core resistive-memory AIMC chips.
  • The paper reports near software-equivalent inference accuracy for ResNet and LSTM networks, including CIFAR-10 image recognition, Penn Treebank character prediction, and Flickr8k image caption generation, with all weight-layer computations and activation functions performed on-chip.

Methods

  • The chip integrates 64 AIMC cores with backend PCM, per-row current-controlled oscillator ADCs, local digital processing units (LDPUs), global digital processing units (GDPUs), and link controllers. Each unit cell uses four PCM devices (two per polarity).
  • MVM accuracy was characterized across all 64 cores using uniformly distributed 30% sparse weight matrices and 2,048 input vectors; errors were decomposed into total, linear (weight programming), and residual contributions. Two closed-loop iterative programming algorithms, ODP and TDP, were compared.
  • DNN inference used hardware-aware training with noise injection on synaptic weights via the IBM Analog Hardware Acceleration Kit. Trained weights were mapped to conductances; ResNet-9, PTB LSTM, and Flickr8k LSTM networks were run with on-chip MVMs, activation functions, batch normalization, LSTM cell-state computation, aggregation, bias addition, and affine scaling. Max-pooling and embeddings were performed in software.

Limitations

  • The paper states that max-pooling in ResNet-9 and character/image/word embedding in the LSTM networks are not supported by the chip and are performed in software.
  • The paper states that PCM conductance drift causes linear and total MVM error to increase over time; TDP shows noticeable residual error due to sampling a wider, more nonlinear ADC range and higher leakage from non-RESET devices.
  • Evident from the provided text: the excerpt is truncated before the full PTB and Flickr8k accuracy results, so those specific numbers cannot be summarized here.

Model-written summary. Check it against the paper before relying on it.

Integrity signals

Registry

Crossref · 10.1038/s41928-023-01010-1

Cites

50 of 50 references verified0 citation errors · 0 not checkable

Statistics

Nothing to recompute.

Claims the paper makes

0 of 1 cited sources checked · 0 supported · 0 flagged

  • Findingown data
    § 30 June 2026

    The chip achieves the highest accuracy on the CIFAR-10 benchmark.

    “while achieving the highest accuracy on the CIFAR-10 benchmark.”
    Quote in the paperSubstantial claim
  • Findingown data
    § IV. MVM ACCURACY148

    The yield of the remaining outlier core is 98.4%.

    “The yield of the remaining outlier core is 98.4%.”
    Quote in the paperNot a substantial claim
  • Findingnone given
    § 30 June 2026

    The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.

    “The fully-integrated chip features 64 256x256 AIMC cores interconnected via an on-chip communication network.”
    Quote in the paperSubstantial claim
  • Findingnone given
    § IV. MVM ACCURACY148

    With TDP, a precision between 3-bit and 4-bit weights is achieved.

    “With TDP, a precision between 3-bit and 4-bit weights is achieved.”
    Quote in the paperSubstantial claim
  • Findingown data
    § IV. MVM ACCURACY148

    When using TDP, ε linear is significantly reduced compared with ODP.

    “When using TDP, ε linear is significantly reduced compared with ODP”
    Quote in the paperSubstantial claim
  • Classified as probably not a substantial claim. 2
  • May combine two claims. 3

  • Probably not a substantial claim: may not pass S3 (load-bearing).

    Findingnone given
    § V. DEEP NEURAL NETWORK INFERENCE DEMONSTRATIONS200

    The LSTM network for PTB character prediction has 1,299,312 weights and 2,066 biases.

    “The LSTM network for PTB character prediction (1,299,312 weights and 2,066 biases)”
    Quote in the paperNot a substantial claim

  • May combine two claims.

    Findingreasoning
    § IV. MVM ACCURACY148

    ε linear and thus also ε total increase over time.

    “ε linear and thus also ε total increase over time as shown in Fig. 2d.”
    Quote in the paperNot a substantial claim

  • May combine two claims.

    Findingnone given
    § 30 June 2026

    The chip implements digital activation functions and processing involved in ResNet convolutional neural networks and LSTM networks.

    “It also implements the digital activation functions and processing involved in ResNet convolutional neural networks and long short-term memory (LSTM) networks.”
    Quote in the paperSubstantial claim

  • Probably not a substantial claim: may not pass S3 (load-bearing).

    Findingnone given
    § V. DEEP NEURAL NETWORK INFERENCE DEMONSTRATIONS200

    The custom ResNet-9 network has 1,866,536 synaptic weights and 10 biases.

    “The custom ResNet-9 network (1,866,536 synaptic weights and 10 biases)”
    Quote in the paperNot a substantial claim

  • May combine two claims.

    Findingown data
    § 30 June 2026

    The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.

    “The chip can achieve a maximal throughput of 63.1 TOPS at an energy efficiency of 9.76 TOPS W−1 for 8-bit input/output matrix-vector multiplications.”
    Quote in the paperSubstantial claim
5 of 5

Claims other papers make about this one

Each is checked against this paper’s own text: does it say what the citing paper says it does?

  • Most advanced studies reported fully integrated memristor-based compute-in-memory systems, but systematic description of essential details on device structure or circuit architecture is generally lacking.

    “The most advanced studies in this field have reported fully integrated memristor-based compute-in-memory systems48,53–55,58,59,61,71–73, but a systematic description of essential details on the device structure or circuit architecture are generally lacking in these reports.”

    From Hardware implementation of memristor-based artificial neural networks (2024) · cites this paper as [73]

    The opening summary and Section I (Chip Architecture) identify this as a fully integrated, 64-core phase-change-memory compute-in-memory chip. But Sections I and II (The Computational Memory Core) describe its architecture and device arrangement, including the core layout, PCM unit cells, and ADC circuitry. This source therefore supports the example of an integrated system, not the suggestion that this report lacks essential architectural details. (LLM, conf=0.86)

    Experimental — accuracy not yet measured

  • A ResNet9 CNN trained with a similar general HWA training approach yielded vastly improved AIMC accuracy in hardware.

    “For instance in a recent study54, a ResNet9 CNN was trained with a similar general HWA training approach yielding vastly improved AIMC accuracy in hardware.”

    From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]

    Section V (page not available) says the ResNet-9 CNN was trained in a hardware-aware manner and achieved 92.81% test accuracy on the AIMC chip, close to the 93.67% software baseline. It does not quantify a vast improvement over a non-hardware-aware training approach or establish that training alone caused such an improvement. (LLM, conf=0.82)

    Experimental — accuracy not yet measured

  • HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.

    “It has been already verified in hardware, however, that HWA training using noise injection is very effective at improving the robustness for selected (smaller) DNNs.”

    From Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators (2023) · cites this paper as [54]

    Section V (lines 200–206) says the three networks were trained with noise injection to improve resilience to hardware nonidealities. The hardware results report near-software accuracy for ResNet-9 (lines 214–225), but the passages do not compare noise-injected training with training without it, so they do not establish how much robustness improved or that noise injection was very effective. (LLM, conf=0.82)

    Experimental — accuracy not yet measured

Cites

Flagged first, then by citations

Research works printed but not linked: 6

  1. Marcus, M. P., Santorini, B. & Marcinkiewicz, M. A. Building a large annotated corpus of English: the Penn Treebank. Comput. Linguist. 19, 313–330 (1993).
  2. Rashtchian, C., Young, P., Hodosh, M. & Hockenmaier, J. Collecting image annotations using Amazon’s mechanical turk. in Proc. NAACL HLT 2010 Workshop on Creating Speech and Language Data with Amazon’s Mechanical Turk CSLDAMT ’10 139–147 (Association for Computational Linguistics, 2010).
  3. Mujika, A., Meier, F. & Steger, A. Fast-slow recurrent neural networks. in Advances in Neural Information Processing Systems Vol. 30 (eds Guyon, I. et al.) (Curran Associates, 2017).
  4. Srivastava, N., Hinton, G., Krizhevsky, A., Sutskever, I. & Salakhutdinov, R. Dropout: a simple way to prevent neural networks from overfitting. J. Mach. Learn. Res. 15, 1929–1958 (2014).
  5. Kingma, D. P. & Ba, J. Adam: a method for stochastic optimization. in 3rd International Conference on Learning Representations, ICLR 2015 (2015).
  6. Ioffe, S. & Szegedy, C. Batch normalization: accelerating deep network training by reducing internal covariate shift. in Proc. 32nd International Conference on International Conference on Machine Learning—Volume 37, ICML’15 448–456 (PMLR, 2015).

Cited by

Sorted by citations

Related

Authors
Le Gallo, M., Khaddam-Aljameh, R., Stanisavljevic, M., Vasilopoulos, A., Kersting, B., Dazzi, M., Karunaratne, G., Brändli, M., Singh, A., Müller, S. M., Büchel, J., Timoneda, X., Joshi, V., Rasch, M. J., Egger, U., Garofalo, A., Petropoulos, A., Antonakopoulos, T., Brew, K., Choi, S., Ok, I., Philip, T., Chan, V., Silvestre, C., Ahsan, I., Saulnier, N., Narayanan, V., Francese, P. A., Eleftheriou, E., & Sebastian, A.
Affiliations
  • IBM Research - Zurich (CH)
  • IBM (Germany) (DE)
  • IBM (United States) (US)
  • University of Patras (GR)
  • IBM Research - Albany (US)
Corresponding author
Sebastian, Abu
ORCID
Venue
Nature Electronics
Publisher
Springer Science and Business Media LLC
Published
2023-08-10
Volume
6
Issue
9
Pages
680-693
ISSN
2520-1131 (ISSN-L)
DOI
10.1038/s41928-023-01010-1
OpenAlex
W4385896568
Semantic Scholar
e28c05440f28c2092a251cf413f2a9d3c90fd1bb
Cited by
310
References
49
Citations by year
2026: 78 · 2025: 130 · 2024: 79 · 2023: 23
FWCI
23.00
Type
journal article
Language
en
Open access
Licence
Locations
  • Nature Electronics (publishedVersion)
  • arXiv (Cornell University) (submittedVersion)
  • Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) (submittedVersion, other-oa)
  • arXiv (Cornell University) (cc-by)
Funders
  • European Commission (HORIZON2020, 682675)
  • H2020 European Research Council (966764)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advanced Memory and Neural Computing
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
  • Physical Sciences › Engineering › Biomedical Engineering › Analog and Mixed-Signal Circuit Design
Keywords
phase-change memory, deep neural network inference, network-on-chip, ResNet, energy efficiency, resistive memory devices

About these checks

Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.

Claims read by deepseek-v4.1-flash under definition version 3 (extract-v3) on 2026-10-07.

Classified by jev-1.13-20260917 (gold-guideline-v0.2) on 2026-10-07.

Statistics and arithmetic are recomputed, not judged.

Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.

What counts as a claim ›How we measure confidence ›How we check this ›

Are you an author, or do you see a problem with this page? Request a review