Schuddinck, Pieter

Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node

Jang, D., Yakimets, D., Eneman, G., Schuddinck, P., Bardon, M. G., Raghavan, P., Spessot, A., Verkest, D., & Mocuta, A. (2017) · IEEE Transactions on Electron Devices

Advancements in Semiconductor Devices and Circuit Design2D Materials and Applications

Cited by 292

The Complementary FET (CFET) for CMOS scaling beyond N3

Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., et al. (2018) · 2018 IEEE Symposium on VLSI Technology

Advancements in Semiconductor Devices and Circuit DesignLow-power high-performance VLSI design

Cited by 262