The DOI matches its Crossref record; 3 of the 3 references it cites were found in a registry or an index.
The Complementary FET (CFET) for CMOS scaling beyond N3
Abstract
The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process flow requires accurate control of the elevation dimension for manufacturability. Based on TCAD analysis, the CFET can eventually outperform the finFET device and meet the N3 targets in power and performance. To achieve that, the dominating parasitic resistance of the deep vias needs to be reduced by the introduction of advanced MOL contacts featuring thin barriers.
Overview
Integrity signals
Registry
Cites
Statistics
Verification
Claims the paper makes
Claims other papers make about this one
Each is checked against this paper’s own text: does it say what the citing paper says it does?
In CFETs, n-channel and p-channel transistors are stacked vertically on top of each other, which can increase performance and density at the expense of processing complexity.
“In these three -dimensional devices, the nchannel and pchannel transistors are stacked vertically on top of each other, which can increase performance and density at the expense of processing complexity 99 .”
From Extreme ultraviolet lithography (2024) · cites this paper as [99]
Citations
Cites
2016 IEEE Symposium on VLSI Technology
(2016) · doi:10.1109/vlsitechnology18215.2016 · Cited by 139
A Three-Dimensional Stacked Fin-CMOS Technology for High-Density ULSI Circuits
Wu, X., Chan, P. C. H., Zhang, S., et al. (2005) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2005.854267 · Cited by 36
2017 IEEE International Reliability Physics Symposium
(2016) · IEEE Transactions on Electron Devices · doi:10.1109/ted.2016.2617295 · Cited by 24
Flagged first, then by citations
Research works printed but not linked: 3
- 0, Comsol Multiphysics
- 0, Coventor SEMulator3D®
- liebmann, 2016, IEEE Symposium on VLSI Technology, 112
Cited by
Sorted by citations
Extreme ultraviolet lithography
Kazazis, D., Santaclara, J. G., van Schoot, J., Mochi, I., & Ekinci, Y. (2024) · Nature Reviews Methods Primers · doi:10.1038/s43586-024-00361-z · Cited by 149
Park, E., & Song, T. (2023) · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · doi:10.1109/tvlsi.2022.3220339 · Cited by 47
Metadata
- Authors
- Ryckaert, J., Schuddinck, P., Weckx, P., Bouche, G., Vincent, B., Smith, J., Sherazi, Y., Mallik, A., Mertens, H., Demuynck, S., Bao, T. H., Veloso, A., Horiguchi, N., Mocuta, A., Mocuta, D., & Boemmels, J.
- Affiliations
- IMEC (BE)
- Tokyo Electron (Japan) (JP)
- Venue
- 2018 IEEE Symposium on VLSI Technology
- Publisher
- IEEE
- Published
- 2018-06
- Pages
- 141-142
- OpenAlex
- W2899004836
- Cited by
- 262
- References
- 3
- Citations by year
- 2026: 58 · 2025: 71 · 2024: 45 · 2023: 29 · 2022: 23 · 2021: 18 · 2020: 10 · 2019: 6 · 2018: 2
- FWCI
- 14.36
- Type
- conference paper
- Language
- en
- Open access
- closed
- Locations
- Symposium on VLSI Technology (publishedVersion)
- Topics
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
- Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor materials and devices
- Keywords
- complementary FET, CFET, CMOS scaling, design-technology co-optimization, FinFET, thin barriers
About these checks
Registry, retraction, Cites and statistics results are computed, not judged, with one exception: a printed reference that no index lists is read once by a model before it counts as a citation error. Claims are extracted by a model and kept only when their quote appears verbatim in the text; each cited source is then checked, with a model’s help, for whether it says what the claim relies on. Those verdicts can be wrong — read the claim’s quote and the cited source before relying on one.
Statistics and arithmetic are recomputed, not judged.
Confidence bands are shown only for fields calibrated on our annotated test set. None is calibrated yet, so no band is shown.
What counts as a claim ›How we measure confidence ›How we check this ›
Are you an author, or do you see a problem with this page? Request a review
