Cited by 100Cryptographic Implementations and SecurityCryptography and Residue ArithmeticEmbedded Systems Design Techniques

An ultra-high throughput and fully pipelined implementation of AES algorithm on FPGA

Soltani, Abolfazl, Sharifian, Saeed·2015·Microprocessors and Microsystems

Integrity signals

Registry

Crossref · 10.1016/j.micpro.2015.07.005

Cites

92 of 92 references verified0 citation errors · 0 not checkable

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Authors
Soltani, A., & Sharifian, S.
Affiliations
Amirkabir University of Technology (IR)
Corresponding author
Soltani, Abolfazl
Venue
Microprocessors and Microsystems
Publisher
Elsevier BV
Published
2015-10
Volume
39
Issue
7
Pages
480-493
ISSN
0141-9331 (ISSN-L)
OpenAlex
W1002902646
Cited by
100
References
92
Citations by year
2026: 6 · 2025: 6 · 2024: 10 · 2023: 9 · 2022: 11 · 2021: 14 · 2020: 11 · 2019: 9 · 2018: 8 · 2017: 5 · 2016: 11
FWCI
7.84
Type
journal article
Language
en
Open access
closed
Locations
Microprocessors and Microsystems (publishedVersion)
Topics
  • Physical Sciences › Computer Science › Artificial Intelligence › Cryptographic Implementations and Security
  • Physical Sciences › Computer Science › Information Systems › Cryptography and Residue Arithmetic
  • Physical Sciences › Computer Science › Hardware and Architecture › Embedded Systems Design Techniques
Keywords
AES, FPGA implementation, S-box, pipelining, loop unrolling, high-throughput encryption, ECB mode, CTR mode, symmetric encryption, area-delay tradeoff

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