A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Deep Residual Learning for Image Recognition

He, K., Zhang, X., Ren, S., & Sun, J. (2016) · 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2016.90 · Cited by 235,474

Very Deep Convolutional Networks for Large-Scale Image Recognition

Simonyan, K., & Zisserman, A. (2014) · arXiv · doi:10.48550/arxiv.1409.1556 · Cited by 114,148

ImageNet classification with deep convolutional neural networks

Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155

Going deeper with convolutions

Szegedy, C., Liu, W., Jia, Y., Sermanet, P., Reed, S., Anguelov, D., Erhan, D., Vanhoucke, V., & Rabinovich, A. (2015) · 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2015.7298594 · Cited by 48,562

ImageNet Large Scale Visual Recognition Challenge

Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al. (2015) · International Journal of Computer Vision · doi:10.1007/s11263-015-0816-y · Cited by 39,380

Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding

Han, S., Mao, H., & Dally, W. J. (2015) · arXiv · doi:10.48550/arxiv.1510.00149 · Cited by 4,662

2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

(2015) · doi:10.1109/cvpr31182.2015 · Cited by 3,826

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158

Proceedings for the 5th International Conference on Learning Representations

Srivastava, A., & Sutton, C. A. (2017) · Cited by 1,829

DaDianNao: A Machine-Learning Supercomputer

Chen, Y., Luo, T., Liu, S., Zhang, S., He, L., Wang, J., Li, L., Chen, T., Xu, Z., Sun, N., et al. (2014) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro.2014.58 · Cited by 1,547

Design possibilities and challenges of DNN models: a review on the perspective of end devices

Hussain, H., Tamizharasan, P. S., & Rahul, C. S. (2022) · Artificial Intelligence Review · doi:10.1007/s10462-022-10138-z · Cited by 118

Embedded Intelligence on FPGA: Survey, Applications and Challenges

Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105

A Full Featured Configurable Accelerator for Object Detection With YOLO

Pestana, D. G., Miranda, P. R., Lopes, J. D., Duarte, R. P., Véstias, M. P., Neto, H. C., & de Sousa, J. T. (2021) · IEEE Access · doi:10.1109/access.2021.3081818 · Cited by 97

A systematic review of computer vision-based personal protective equipment compliance in industry practice: advancements, challenges and future directions

Vukićević, A. M., Petrovic, M., Milošević, P., Peulić, A., Jovanovic, K. M., & Novakovic, A. (2024) · Artificial Intelligence Review · doi:10.1007/s10462-024-10978-x · Cited by 76

Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction

Wardana, I. N. K., Gardner, J. W., & Fahmy, S. A. (2021) · Sensors · doi:10.3390/s21041064 · Cited by 61

Artificial neural network-based DTC of an induction machine with experimental implementation on FPGA

Gdaim, S., Mtibaa, A., & Mimouni, M. F. (2023) · Engineering Applications of Artificial Intelligence · doi:10.1016/j.engappai.2023.105972 · Cited by 30

Real-Time Multi-Task ADAS Implementation on Reconfigurable Heterogeneous MPSoC Architecture

Tatar, G., & Bayar, S. (2023) · IEEE Access · doi:10.1109/access.2023.3300379 · Cited by 28

Electronic Nose Pattern Recognition Engine: Design, Build, and Deployment

Sun, F., Wu, B., Jia, Y., Duan, S., & Hu, X. (2022) · IEEE Sensors Journal · doi:10.1109/jsen.2022.3225535 · Cited by 17

Configurable 2D–3D CNNs Accelerator for FPGA-Based Hyperspectral Imagery Classification

He, W., Yang, Y., Mei, S., Hu, J., Xu, W., & Hao, S. (2023) · IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing · doi:10.1109/jstars.2023.3321965 · Cited by 17

Power Efficient Real-Time Traffic Signal Classification for Autonomous Driving Using FPGAs

Amin, R. A., Hossain, M. S. A., Schmid, L. T., Wiese, V., & Obermaisser, R. (2024) · International Conference on Communications, Signal Processing, and their Applications (ICCSPA) · doi:10.1109/iccspa61559.2024.10794303 · Cited by 15

Smart Embedded System for Skin Cancer Classification

Durães, P. F., & Véstias, M. P. (2023) · Future Internet · doi:10.3390/fi15020052 · Cited by 14

Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs

Wan, Y., Xie, X., Yi, L., Jiang, B., Chen, J., & Jiang, Y. (2024) · Journal of Systems Architecture · doi:10.1016/j.sysarc.2024.103113 · Cited by 17

Efficient Design of Pruned Convolutional Neural Networks on FPGA

Véstias, M. P. (2020) · Journal of Signal Processing Systems · doi:10.1007/s11265-020-01606-2 · Cited by 13

Configurable Hardware Core for IoT Object Detection

Miranda, P. R., Pestana, D. G., Lopes, J. D., Duarte, R. P., Véstias, M. P., Neto, H. C., & de Sousa, J. T. (2021) · Future Internet · doi:10.3390/fi13110280 · Cited by 11

Performance Evaluation of Low-Precision Quantized LeNet and ConvNet Neural Networks

Tatar, G., Bayar, S., & Çiçek, İ. (2022) · International Conference on Innovations in Intelligent Systems and Applications (INISTA) · doi:10.1109/inista55318.2022.9894261 · Cited by 12

HePiLUT: Resource Efficient Heterogeneous Pipelined CNN Accelerator for FPGAs

Amin, R. A., Hossain, M. S. A., & Obermaisser, R. (2024) · International Conference on Intelligent Computing, Communication, Networking and Services (ICCNS) · doi:10.1109/iccns62192.2024.10776054 · Cited by 9

Designing Deep Learning Models on FPGA with Multiple Heterogeneous Engines

Reis, M., Véstias, M. P., & Neto, H. C. (2023) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3615870 · Cited by 7

Efficient Design of Low Bitwidth Convolutional Neural Networks on FPGA with Optimized Dot Product Units

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2022) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3546182 · Cited by 7

Towards Resource Efficient and Low Latency CNN Accelerator for FPGAs: Review and Evaluation

Amin, R. A., & Obermaisser, R. (2024) · International Conference on Embedded Systems and Artificial Intelligence (ESAI) · doi:10.1109/esai62891.2024.10913881 · Cited by 6

On the Use of FPGAs to Implement CNNs: A Brief Review

Arshad, M., Shahriar, S., & Sagahyroon, A. A. (2020) · International Conference on Computing, Electronics & Communications Engineering (iCCECE) · doi:10.1109/iccece49321.2020.9231243 · Cited by 5

An Embedded Intelligent System for Real-Time Image Classification with a Neuro-Inspired Color Constancy Algorithm

Morita, A., & Okuno, H. (2024) · IEICE Transactions on Electronics · doi:10.1587/transele.2024lhp0003 · Cited by 3

Triple Fixed-Point MAC Unit for Deep Learning

Kerner, M., Tammemäe, K., Raik, J., & Hollstein, T. (2021) · Design, Automation, and Test in Europe · doi:10.23919/date51398.2021.9474020 · Cited by 1

MRSA: A multi-mode reconfigurable systolic array architecture based on channel-wise stationary dataflow for CNNs

Zhang, X., Song, X., Liu, S., Liu, Y., & Gao, J. S. (2025) · Microelectronics Journal · doi:10.1016/j.mejo.2025.106983 · Cited by 1

FPGA Based Military Vehicle Classification from Drone-Based Video Using Deep Learning

Vasavi, S., Sowmya, D., Aishwarya, C., & Flores‐Fuentes, W. (2024) · International Conference on Frontiers of Signal Processing (ICFSP) · doi:10.1109/icfsp62546.2024.10785445 · Cited by 1

Machine Learning

Bailey, D. G. (2023) · doi:10.1002/9781119819820.ch14 · Cited by 1

Hardware Architecture

Hung, P., Kan, H., & Knopf, G. (2024) · doi:10.1002/9781119813873.ch5 · Cited by 1

A Comparative Study of Neural Network and Fuzzy Logic Controller Approaches for BLDC Motor Speed Control

Megrini, M., Gaga, A., & Mehdaoui, Y. (2025) · Communications in computer and information science · doi:10.1007/978-3-031-93448-3_25

The Role of Computational Parallelism in Artificial Intelligence Learning Models

Sousa, C., Couto, P., Rocha, G. A., Quintas, J. M., & Lopes, S. (2026) · Springer eBooks · doi:10.1007/978-3-031-99147-9_20

Multi-Channel Spatial Representation Learning for FPGA Routability Prediction

Cai, L., & Xu, N. (2025) · International Conference on Electronic Information Engineering and Computer Communication (EIECC) · doi:10.1109/eiecc67963.2025.11409637

Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2019) · Electronics · doi:10.3390/electronics8111321 · Cited by 19

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2018) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl.2018.00075 · Cited by 19

Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning

Peres, T., Gonçalves, A., & Véstias, M. P. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-17227-5_28 · Cited by 8

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs

Gonçalves, A., Peres, T., & Véstias, M. P. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-17227-5_27 · Cited by 7

Efficient Design of Pruned Convolutional Neural Networks on FPGA

Véstias, M. P. (2020) · Journal of Signal Processing Systems · doi:10.1007/s11265-020-01606-2 · Cited by 13