A fast and scalable architecture to run convolutional neural networks in low density FPGAs

Deep Residual Learning for Image Recognition

He, K., Zhang, X., Ren, S., & Sun, J. (2016) · 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2016.90 · Cited by 235,474

Very Deep Convolutional Networks for Large-Scale Image Recognition

Simonyan, K., & Zisserman, A. (2014) · arXiv · doi:10.48550/arxiv.1409.1556 · Cited by 114,148

ImageNet classification with deep convolutional neural networks

Krizhevsky, A., Sutskever, I., & Hinton, G. E. (2017) · Communications of the ACM · doi:10.1145/3065386 · Cited by 112,155

Going deeper with convolutions

Szegedy, C., Liu, W., Jia, Y., Sermanet, P., Reed, S., Anguelov, D., Erhan, D., Vanhoucke, V., & Rabinovich, A. (2015) · 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR) · doi:10.1109/cvpr.2015.7298594 · Cited by 48,562

ImageNet Large Scale Visual Recognition Challenge

Russakovsky, O., Deng, J., Su, H., Krause, J., Satheesh, S., Ma, S., Huang, Z., Karpathy, A., Khosla, A., Bernstein, M., et al. (2015) · International Journal of Computer Vision · doi:10.1007/s11263-015-0816-y · Cited by 39,380

Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding

Han, S., Mao, H., & Dally, W. J. (2015) · arXiv · doi:10.48550/arxiv.1510.00149 · Cited by 4,662

2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR)

(2015) · doi:10.1109/cvpr31182.2015 · Cited by 3,826

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks

Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., & Cong, J. (2015) · Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/2684746.2689060 · Cited by 2,158

Proceedings for the 5th International Conference on Learning Representations

Srivastava, A., & Sutton, C. A. (2017) · Cited by 1,829

DaDianNao: A Machine-Learning Supercomputer

Chen, Y., Luo, T., Liu, S., Zhang, S., He, L., Wang, J., Li, L., Chen, T., Xu, Z., Sun, N., et al. (2014) · IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro.2014.58 · Cited by 1,547

Going Deeper with Embedded FPGA Platform for Convolutional Neural Network

Qiu, J., Wang, J., Yao, S., Guo, K., Li, B., Zhou, E., Yu, J., Tang, T., Xu, N., Song, S., et al. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847265 · Cited by 1,290

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Umuroglu, Y., Fraser, N. J., Gambardella, G., Blott, M., Leong, P., Jahre, M., & Vissers, K. (2017) · Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays · doi:10.1145/3020078.3021744 · Cited by 1,189

Fused-layer CNN accelerators

Alwani, M., Chen, H., Ferdman, M., & Milder, P. (2016) · 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) · doi:10.1109/micro.2016.7783725 · Cited by 662

Cnvlutin

Albericio, J., Judd, P., Hetherington, T., Aamodt, T. M., Jerger, N. E., & Moshovos, A. (2016) · ACM SIGARCH Computer Architecture News · doi:10.1145/3007787.3001138 · Cited by 620

Angel-Eye: A Complete Design Flow for Mapping CNN Onto Embedded FPGA

Guo, K., Sui, L., Qiu, J., Yu, J., Wang, J., Yao, S., Han, S., Wang, Y., & Yang, H. (2017) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2017.2705069 · Cited by 559

Throughput-Optimized OpenCL-based FPGA Accelerator for Large-Scale Convolutional Neural Networks

Suda, N., Chandra, V., Dasika, G. S., Mohanty, A., Ma, Y., Vrudhula, S. B. K., Seo, J.-S., & Cao, Y. K. (2016) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/2847263.2847276 · Cited by 556

Handwritten digit recognition: applications of neural network chips and automatic learning

Le Cun, Y., Jackel, L. D., Boser, B., Denker, J. S., Graf, H. P., Guyon, I., Henderson, D., Howard, R. E., & Hubbard, W. (1989) · IEEE Communications Magazine · doi:10.1109/35.41400 · Cited by 480

A dynamically configurable coprocessor for convolutional neural networks

Chakradhar, S., Sankaradas, M., Jakkula, V., & Cadambi, S. (2010) · Proceedings of the 37th annual international symposium on Computer architecture · doi:10.1145/1815961.1815993 · Cited by 343

FP-BNN: Binarized neural network on FPGA

Liang, S., Yin, S., Liu, L., Luk, W. W., & Wei, S. (2017) · Neurocomputing · doi:10.1016/j.neucom.2017.09.046 · Cited by 307

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Shen, Y., Ferdman, M., & Milder, P. A. (2017) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/3079856.3080221 · Cited by 291

Hardware-oriented Approximation of Convolutional Neural Networks

Gysel, P., Motamedi, M., & Ghiasi, S. (2016) · arXiv · doi:10.48550/arxiv.1604.03168 · Cited by 287

Scalpel

Yu, J., Lukefahr, A., Palframan, D. J., Dasika, G. S., Das, R., & Mahlke, S. A. (2017) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1145/3079856.3080215 · Cited by 281

Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing

Albericio, J., Judd, P., Hetherington, T., Aamodt, T. M., Jerger, N. E., & Moshovos, A. (2016) · Proceedings - International Symposium on Computer Architecture/Proceedings · doi:10.1109/isca.2016.11 · Cited by 266

Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural Network

Zhang, J., & Li, J. (2017) · ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA) · doi:10.1145/3020078.3021698 · Cited by 212

Design space exploration of FPGA-based Deep Convolutional Neural Networks

Motamedi, M., Gysel, P., Akella, V., & Ghiasi, S. (2016) · Asia and South Pacific Design Automation Conference (ASP-DAC) · doi:10.1109/aspdac.2016.7428073 · Cited by 211

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

(2016) · doi:10.1109/micro37956.2016 · Cited by 188

fpgaConvNet: Mapping regular and irregular convolutional neural networks on FPGAs

Venieris, S. I., & Bouganis, C.-S. (2019) · IEEE Transactions on Neural Networks and Learning Systems · doi:10.1109/tnnls.2018.2844093 · Cited by 161

A dynamically configurable coprocessor for convolutional neural networks

Chakradhar, S., Sankaradas, M., Jakkula, V., & Cadambi, S. (2010) · ACM SIGARCH Computer Architecture News · doi:10.1145/1816038.1815993 · Cited by 154

Scalpel

Yu, J., Lukefahr, A., Palframan, D. J., Dasika, G. S., Das, R., & Mahlke, S. A. (2017) · ACM SIGARCH Computer Architecture News · doi:10.1145/3140659.3080215 · Cited by 152

MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip

Gong, L., Wang, C., Li, X., Chen, H., & Zhou, X. (2018) · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · doi:10.1109/tcad.2018.2857078 · Cited by 118

Throughput-Optimized FPGA Accelerator for Deep Convolutional Neural Networks

Liu, Z.-Q., Dou, Y., Jiang, J., Xu, J., Li, S., Zhou, Y., & Xu, Y. (2017) · ACM Transactions on Reconfigurable Technology and Systems · doi:10.1145/3079758 · Cited by 117

Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA

Wang, J., Lou, Q., Zhang, X., Zhu, C., Lin, Y., & Chen, D. (2018) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl.2018.00035 · Cited by 109

Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer

Shen, Y., Ferdman, M., & Milder, P. A. (2017) · IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) · doi:10.1109/fccm.2017.47 · Cited by 102

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

Santambrogio, M. D., Göhringer, D., Stroobandt, D., Mentens, N., & Nurmi, J. (2017) · doi:10.23919/fpl41764.2017 · Cited by 85

FINN: A Framework for Fast, Scalable Binarized Neural Network Inference

Umuroglu, Y., Fraser, N. J., Gambardella, G., Blott, M., Leong, P. H. W., Jahre, M., & Vissers, K. (2016) · NORA - Norwegian Open Research Archives · doi:10.48550/arxiv.1612.07119 · Cited by 79

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

(2014) · doi:10.1109/micro33565.2014 · Cited by 76

2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)

(2016) · doi:10.1109/asp-dac36859.2016 · Cited by 63

2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)

(2016) · doi:10.1109/isca36197.2016 · Cited by 60

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Walters, E. (2016) · Computers · doi:10.3390/computers5040020 · Cited by 55

FPGA‐accelerated deep convolutional neural networks for high throughput and energy efficiency

Qiao, Y., Shen, J., Xiao, T., Yang, Q., Wen, M., & Zhang, C. (2016) · Concurrency and Computation Practice and Experience · doi:10.1002/cpe.3850 · Cited by 50

2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

(2018) · doi:10.1109/fccm42140.2018 · Cited by 41

Parallel dot-products for deep learning on FPGA

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2017) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.23919/fpl.2017.8056863 · Cited by 28

Design possibilities and challenges of DNN models: a review on the perspective of end devices

Hussain, H., Tamizharasan, P. S., & Rahul, C. S. (2022) · Artificial Intelligence Review · doi:10.1007/s10462-022-10138-z · Cited by 118

Embedded Intelligence on FPGA: Survey, Applications and Challenges

Seng, K. P., Lee, P. J., & Ang, L. M. (2021) · Electronics · doi:10.3390/electronics10080895 · Cited by 105

A Full Featured Configurable Accelerator for Object Detection With YOLO

Pestana, D. G., Miranda, P. R., Lopes, J. D., Duarte, R. P., Véstias, M. P., Neto, H. C., & de Sousa, J. T. (2021) · IEEE Access · doi:10.1109/access.2021.3081818 · Cited by 97

A systematic review of computer vision-based personal protective equipment compliance in industry practice: advancements, challenges and future directions

Vukićević, A. M., Petrovic, M., Milošević, P., Peulić, A., Jovanovic, K. M., & Novakovic, A. (2024) · Artificial Intelligence Review · doi:10.1007/s10462-024-10978-x · Cited by 76

Optimising Deep Learning at the Edge for Accurate Hourly Air Quality Prediction

Wardana, I. N. K., Gardner, J. W., & Fahmy, S. A. (2021) · Sensors · doi:10.3390/s21041064 · Cited by 61

Fast Convolutional Neural Networks in Low Density FPGAs Using Zero-Skipping and Weight Pruning

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2019) · Electronics · doi:10.3390/electronics8111321 · Cited by 19

Lite-CNN: A High-Performance Architecture to Execute CNNs in Low Density FPGAs

Véstias, M. P., Duarte, R. P., de Sousa, J. T., & Neto, H. C. (2018) · International Conference on Field Programmable Logic and Applications (FPL) · doi:10.1109/fpl.2018.00075 · Cited by 19

Faster Convolutional Neural Networks in Low Density FPGAs Using Block Pruning

Peres, T., Gonçalves, A., & Véstias, M. P. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-17227-5_28 · Cited by 8

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs

Gonçalves, A., Peres, T., & Véstias, M. P. (2019) · Lecture notes in computer science · doi:10.1007/978-3-030-17227-5_27 · Cited by 7

Efficient Design of Pruned Convolutional Neural Networks on FPGA

Véstias, M. P. (2020) · Journal of Signal Processing Systems · doi:10.1007/s11265-020-01606-2 · Cited by 13