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Cited by 334VLSI and FPGA Design TechniquesCopper Interconnects and ReliabilityInterconnection Networks and Systems

The DOI matches its Crossref record, with a small difference in title or year; 1 of the 1 references it cites were found in a registry or an index.

Performance optimization of VLSI interconnect layout

Cong, Jason, He, Lei, Koh, Cheng-Kok, Madden, Patrick H.·1996·Integration
DOI 10.1016/s0167-9260(96)00008-9
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Metadata

Authors
Cong, J., He, L., Koh, C.-K., & Madden, P. H.
Affiliations
University of California, Los Angeles (US)
Corresponding author
Cong, Jason
ORCID
Venue
Integration
Publisher
Elsevier BV
Published
1996-11
Volume
21
Issue
1-2
Pages
1-94
ISSN
0167-9260 (ISSN-L)
DOI
10.1016/s0167-9260(96)00008-9
OpenAlex
W2076265641
Cited by
334
References
1
Citations by year
2025: 1 · 2024: 2 · 2023: 1 · 2022: 1 · 2021: 4 · 2019: 6 · 2018: 5 · 2017: 4 · 2016: 3 · 2015: 3 · 2014: 6 · 2013: 6 · 2012: 10
FWCI
24.24
Type
journal article
Language
en
Open access
closed
Licence
Locations
Integration (publishedVersion)
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › VLSI and FPGA Design Techniques
  • Physical Sciences › Materials Science › Electronic, Optical and Magnetic Materials › Copper Interconnects and Reliability
  • Physical Sciences › Computer Science › Computer Networks and Communications › Interconnection Networks and Systems
Keywords
topology optimization, wirelength minimization, delay reduction, device sizing, buffer insertion, clock routing, physical design

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