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Cited by 90Advancements in Semiconductor Devices and Circuit DesignSemiconductor materials and devicesLow-power high-performance VLSI design

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Analytical model for threshold voltage and I–V characteristics of fully depleted short channel cylindrical/surrounding gate MOSFET

Kranti, Abhinav, Haldar, S., Gupta, R.S.·2001·Microelectronic Engineering
DOI 10.1016/s0167-9317(00)00419-6
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Research works printed but not linked: 21

  1. Kimura, 1986, Power reduction techniques in megabit DRAM’s, IEEE J. Solid State Circuits, 21, 381, 10.1109/JSSC.1986.1052538 · DOI
  2. C. Hu, Hot electron effects in MOSFET’s, IEDM Tech. Dig. (1983) 176–179. · DOI
  3. Ohno, 1995, 0.25-μm gate fully depleted CMOS/SIMOX process using a experimental new two step LOCOS isolation technique, IEEE Trans. Electron Devices, 42, 1481, 10.1109/16.398663 · DOI
  4. Hsio, 1995, Subthreshold characteristics of fully depleted submicrometer SOI MOSFET’s, IEEE Trans. Electron Devices, 42, 1120, 10.1109/16.387246 · DOI
  5. Francis, 1994, Modeling of ultrathin double-gate nMOS/SOI transistors, IEEE Trans. Electron Devices, 41, 715, 10.1109/16.285022 · DOI
  6. Fiegna, 1994, Scaling the MOS transistor below 0.1 μm: methodology, device structure and technology requirements, IEEE Trans. Electron Devices, 41, 941, 10.1109/16.293306 · DOI
  7. H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, F. Masuoka, High performance CMOS surrounding gate transistor (SGT) for ultra high density LSI’s, IEDM Tech. Dig. (1988) 222. · DOI
  8. Takato, 1991, Impact of surrounding gate transistor (SGT) for ultra high density LSI’s, IEEE Trans. Electron Devices, 38, 573, 10.1109/16.75168 · DOI
  9. K. Sunnouchi, H. Takato, N. Okaba, T. Yamada, T. Ozaki, S. Inoue, K. Hashimoto, K. Hieda, A. Nitayama, F. Horiguchi, F. Masuoka, A surrounding gate transistor (SGT) cell 64/256Mbit DRAMs, IEDM Tech. Dig. (1989) 23. · DOI
  10. Watanabe, 1995, A novel circuit technology with surrounding gate transistors (SGT) for ultra-high density DRAM’s, IEEE J. Solid State Circuits, 30, 960, 10.1109/4.406391 · DOI
  11. Maeda, 1995, Impact of a vertical Φ-shaped transistor (VΦT) cell for 1 Gbit DRAM and beyond, IEEE Trans. Electron Devices, 42, 2117, 10.1109/16.477769 · DOI
  12. Nitayama, 1991, Multi-pillar surrounding gate transistor (M-SGT) for compact and high speed circuits, IEEE Trans. Electron Devices, 38, 579, 10.1109/16.75169 · DOI
  13. Auth, 1997, Scaling theory for cylindrical fully-depleted, surrounding gate MOSFET’s, IEEE Electron Device Lett., 18, 74, 10.1109/55.553049 · DOI
  14. Miyano, 1992, Numerical analysis of a cylindrical thin-pillar transistor (CYNTHIA), IEEE Trans. Electron Devices, 39, 1876, 10.1109/16.144678 · DOI
  15. Jang, 1998, An analytical surrounding gate MOSFET model, Solid State Electronics, 42, 721, 10.1016/S0038-1101(97)00243-8 · DOI
  16. Endoh, 1997, An accurate model of fully-depleted surrounding gate transistor (FD-SGT), IEICE Trans. Electron., E80-C, 905
  17. Endoh, 1997, An analytical steady state-steady current-voltage characteristics of short channel fully depleted surrounding gate transistor (FD-SGT), IEICE Trans. Electron., E80-C, 911
  18. Young, 1989, Analysis of conduction in fully depleted SOI MOSFET’s, IEEE Trans. Electron Devices, 36, 504, 10.1109/16.19960 · DOI
  19. Yan, 1992, Scaling the Si MOSFET: from bulk to SOI to bulk, IEEE Trans. Electron Devices, 39, 1704, 10.1109/16.141237 · DOI
  20. Suzuki, 1996, Analytical threshold voltage model for short channel n+–p+ double gate SOI MOSFET’s, IEEE Trans. Electron Devices, 43, 732, 10.1109/16.491249 · DOI
  21. Aggarwal, 1994, Analytical two-dimensional modeling for potential distribution and threshold voltage of short channel fully depleted SOI MOSFETs, Solid State Electronics, 37, 1537, 10.1016/0038-1101(94)90162-7 · DOI

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Metadata

Authors
Kranti, A., Haldar, S., & Gupta, R. S.
Affiliations
University of Delhi (IN)
Corresponding author
Kranti, Abhinav
ORCID
Venue
Microelectronic Engineering
Publisher
Elsevier BV
Published
2001-08
Volume
56
Issue
3-4
Pages
241-259
ISSN
0167-9317 (ISSN-L)
DOI
10.1016/s0167-9317(00)00419-6
OpenAlex
W2010332910
Cited by
90
References
0
Citations by year
2026: 1 · 2025: 5 · 2024: 2 · 2023: 6 · 2022: 2 · 2021: 6 · 2020: 4 · 2019: 5 · 2018: 7 · 2017: 2 · 2016: 8 · 2015: 4 · 2014: 5 · 2013: 5 · 2012: 3
FWCI
0.40
Type
journal article
Language
en
Open access
closed
Licence
www.elsevier.com/tdm/userlicense/1.0/ (tdm)
Locations
Microelectronic Engineering (publishedVersion)
Funders
Defence Research and Development Organisation
Topics
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Advancements in Semiconductor Devices and Circuit Design
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Semiconductor materials and devices
  • Physical Sciences › Engineering › Electrical and Electronic Engineering › Low-power high-performance VLSI design
Keywords
threshold voltage, current-voltage characteristics, short-channel MOSFET, surrounding-gate MOSFET, fully depleted SOI, field-dependent mobility, velocity saturation, source/drain resistance, analytical model

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